/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/********************************************************************************************************
 * \file     Adc_Ip.c
 * \brief    AUTOSAR 4.3.1 MCAL Adc Ip level driver
 *
 * <table>
 * <tr><th>Date           <th>Version
 * <tr><td>2023/07/28     <td>1.0.0
 * </table>
 *******************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/********************************************************************************************************
 *                       Include header files
 *******************************************************************************************************/
#include "Adc_Ip.h"
#include "Adc.h"
#include "Adc_Types.h"
#include "Adc_ConfigTypes.h"
#include "Adc_Cfg.h"
/** Traceability    :   SWSR_ADC_032    */
#include "Std_Types.h"
#include "Adc_reg.h"
#include "SchM_Adc.h"
#include "RegHelper.h"
#include "Adc_Fault.h"
#include "Mcal.h"
#if (ADC_DMA_SUPPORTED == STD_ON)
#include "Mcal_Soc.h"
#include "Mcal_Cache.h"
#include "Dma.h"
#endif /* #if (ADC_DMA_SUPPORTED == STD_ON) */

/********************************************************************************************************
 *                           Private Variable Definitions
 *******************************************************************************************************/

#if (ADC_DMA_SUPPORTED == STD_ON) /* AdcEnableDmaTransferMode enabled */
#if (ADC_NO_CACHEABLE_NEEDED == STD_ON)
#define ADC_START_SEC_VAR_NO_INIT_NO_CACHE_UNSPECIFIED
#else
#define ADC_START_SEC_VAR_NO_INIT_UNSPECIFIED
#endif /** #if (ADC_NO_CACHEABLE_NEEDED == STD_ON) */
#include "Adc_MemMap.h"
/* ADC_CACHE_LINE * 2 used purpose: To ensure the alignment of the cache line in multi-core situation,
    the valid length value is ADC_DMA_PER_GROUP_MAX_VALUE_CNT(40) */
/* PRQA S 1840,1843,3494  5 */
static VAR_ALIGN(Adc_ValueGroupType
                 Adc_DmaBufAdcUnit[ADC_MODULE_NUMBER * ADC_DMA_PER_UNIT_CHNL_CNT]
                 [ADC_CACHE_ALIGN_SIZE((ADC_DMA_PER_GROUP_MAX_VALUE_CNT))],
                 ADC_CACHE_LINE);
#if (ADC_NO_CACHEABLE_NEEDED == STD_ON)
#define ADC_STOP_SEC_VAR_NO_INIT_NO_CACHE_UNSPECIFIED
#else
#define ADC_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#endif /** #if (ADC_NO_CACHEABLE_NEEDED == STD_ON) */
#include "Adc_MemMap.h"

#define ADC_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Adc_MemMap.h"
/* ADC_CACHE_LINE used purpose: To ensure the alignment of the cache line in multi-core situation,
    the valid length value is ADC_DMA_PER_UNIT_CHNL_CNT(2) */
/* PRQA S 1840,1843,3494  5 */
static VAR_ALIGN(boolean
                 Adc_DmaTransStatus[ADC_MODULE_NUMBER][ADC_CACHE_ALIGN_SIZE(ADC_DMA_PER_UNIT_CHNL_CNT)],
                 ADC_CACHE_LINE);
#define ADC_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Adc_MemMap.h"

#define ADC_START_SEC_CONST_UNSPECIFIED
#include "Adc_MemMap.h"
/*PRQA S 3218 2*/
/* dma adc table value table (readonly) */
static const Dma_PeripheralIdType Adc_DmaUnitTable[ADC_MODULE_NUMBER] = {
                                                                    DMA_ADC1,
                                                                    DMA_ADC2,
                                                                    DMA_ADC3,
                                                                    DMA_ADC4,
                                                                    DMA_ADC5,
                                                                    DMA_ADC6,
                                                                    DMA_ADC7};
/*PRQA S 3218 2*/
/* dma adc fifo table (readonly) */
static const Dma_SubIdType Adc_DmaSubIdTable[ADC_DMA_PER_UNIT_CHNL_CNT] = {
                                                                    DMA_ADC_FIFO0,
                                                                    DMA_ADC_FIFO1};
#define ADC_STOP_SEC_CONST_UNSPECIFIED
#include "Adc_MemMap.h"
#endif /* AdcEnableDmaTransferMode enabled */

#define ADC_START_SEC_CONST_32
#include "Adc_MemMap.h"
/* adc unit base address */
static const Adc_RegisterBaseType Adc_BaseAddress[ADC_MODULE_NUMBER] = {
                                                            ADC1_BASE_ADDRESS,
                                                            ADC2_BASE_ADDRESS,
                                                            ADC3_BASE_ADDRESS,
                                                            ADC4_BASE_ADDRESS,
                                                            ADC5_BASE_ADDRESS,
                                                            ADC6_BASE_ADDRESS,
                                                            ADC7_BASE_ADDRESS};
#define ADC_STOP_SEC_CONST_32
#include "Adc_MemMap.h"

#if (ADC_DMA_SUPPORTED == STD_ON)
static Adc_ErrorIdType Adc_Ip_StartDmaTransmission(Adc_GroupType dmaGroup);
static Adc_ErrorIdType Adc_Ip_StopDmaTransmission(Adc_GroupType dmaGroup);
#endif /* #if (ADC_DMA_SUPPORTED == STD_ON) */
static Adc_ErrorIdType Adc_Ip_ChnlValueHandle(Adc_RegisterBaseType unitBase, Adc_GroupType grpId,
        const Adc_ValueGroupType *checkValue);
static void Adc_ClearIntEnableAndStatus(Adc_RegisterBaseType hwUnitbase, Adc_RegisterValue regVal);

/* fast code function 1 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function write the register.

 * \verbatim
 * Syntax             : static void Adc_WriteRegister(volatile uint32 address, uint8 startBit,
 *                                                      uint8 bitWidth, uint32 value)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : address - register address
                        startBit - start bit position
                        bitWidth - width of the target bit field
                        value    - value to write into the register

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ADC_E_UNINIT: Adc driver is not initialized
 *                      Others: No error

 * Description        : This function write the register.
 * \endverbatim
 * Traceability       :
 *******************************************************************************************************/
static void Adc_WriteRegister(volatile uint32 address, uint8 startBit, uint8 bitWidth,
                              uint32 value)
{
    /* #10 get register current value */
    uint32 tempValue = *((volatile uint32 *)(address));
    /* #20 reset bit field which is ready to modify */

    tempValue &= ~(ADC_BITFIELD_MASK(bitWidth) << startBit);
    /* #30 modify tartge bit field */

    tempValue |= (value << startBit) & (ADC_BITFIELD_MASK(bitWidth) << startBit);
    /* #40 writer register */
    *((volatile uint32 *)(address)) = tempValue;
}
/* fast code function 1 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 2 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function checks whether Adc driver has been initialized.

 * \verbatim
 * Syntax             : Adc_ErrorIdType Adc_CheckInitNotYet(
 *                          void)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : None

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ADC_E_UNINIT: Adc driver is not initialized
 *                      Others: No error

 * Description        : This function checks whether Adc driver has been initialized.
 * \endverbatim
 * Traceability       : SWSR_ADC_064 SWSR_ADC_072 SWSR_ADC_082 SWSR_ADC_094
 *                      SWSR_ADC_103 SWSR_ADC_109 SWSR_ADC_115 SWSR_ADC_122
 *                      SWSR_ADC_130 SWSR_ADC_137 SWSR_ADC_143 SWSR_ADC_146
 *                      SWSR_ADC_150 SWSR_ADC_177 SWSR_ADC_189 SWSR_ADC_190
 *                      SW_SM001
 *******************************************************************************************************/
Adc_ErrorIdType Adc_CheckInitNotYet(void)
{
    Adc_ErrorIdType errorStatus = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    /* #10 check whether Adc has been initialized. */
    if (ADC_GLOBAL_STATE_UNINIT == Adc_Handler[coreId]->globalInitState)
    {
        errorStatus = ADC_E_UNINIT;
    } /* else not needed */

    return errorStatus;
}
/* fast code function 2 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"


#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function checks whether Adc interrupt enable bit is set.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_InterruptEnableCheck(
 *                          Adc_RegisterBaseType unitBase)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : unitBase - ADC unit base address

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errorStatus:
 *                      0: No Error
 *                      ADC_E_INT_NOT_ENABLE: Interrupt bit not enable.

 * Description        : This function checks whether Adc interrupt enable bit is set.
 * \endverbatim
 * Traceability       : SW_SM004
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_InterruptEnableCheck(Adc_RegisterBaseType unitBase)
{
    Adc_ErrorIdType errorStatus = 0U;
    AdcFaultInj_Adc_InterruptEnableCheckIntSta(unitBase);
    AdcFaultInj_Adc_InterruptEnableCheckIntSig(unitBase);
    /* only sub fifo water mark interrupt is expected */
    if (FALSE == (REG_READ32(unitBase + SADC_INT_SIG_EN_BASE) & SADC_INT_SIG_EN_SUB_FIFO_ALL))
    {
        errorStatus = ADC_E_INT_NOT_ENABLE;
    }
    else if (FALSE == (REG_READ32(unitBase + SADC_INT_STA_EN_BASE) & SADC_INT_STA_EN_SUB_FIFO_ALL))
    {
        errorStatus = ADC_E_INT_NOT_ENABLE;
    }
    else
    {
        /* do nothing */
    }

    return errorStatus;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function get HwCfg.

 * \verbatim
 * Syntax             : static const Adc_HwUnitConfigType *Adc_GetHwCfgThroughPhysicalId(
 *                                                                          Adc_HwUnitType hwPhysicalId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : hwPhysicalId

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function get HwCfg.
 * \endverbatim
 *******************************************************************************************************/
static const Adc_HwUnitConfigType *Adc_GetHwCfgThroughPhysicalId(Adc_HwUnitType hwPhysicalId)
{
    Adc_HwUnitType hwUnitIndex = 0U;
    const Adc_HwUnitConfigType *tempHwCfg = NULL_PTR;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    for (; hwUnitIndex < coreHandlerPtr->globalConfigPtr->unitCount; hwUnitIndex++)
    {
        if ((hwPhysicalId == (Adc_HwUnitType)coreHandlerPtr->globalConfigPtr->adcUnitCfgPtr[hwUnitIndex].hwModulePhysicalId) &&
            (coreId == coreHandlerPtr->globalConfigPtr->adcUnitCfgPtr[hwUnitIndex].coreAllocatedUint))
        {
            tempHwCfg = &(coreHandlerPtr->globalConfigPtr->adcUnitCfgPtr[hwUnitIndex]);
            break;
        } /* else not needed */
    }

    AdcFaultInj_Adc_GetHwCfgThroughPhysicalIdGetNull();
    return tempHwCfg;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function get InterruptBit.

 * \verbatim
 * Syntax             : static Adc_RcRchtIndexType Adc_Ip_GetInterruptBit(Adc_RegisterBaseType unitBase)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : unitBase

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function get InterruptBit.
 * \endverbatim
 *******************************************************************************************************/
static uint8 Adc_Ip_GetInterruptBit(Adc_RegisterBaseType unitBase)
{
    uint32 registerValue;
    uint8 interruptBits;
    /* #10 get interrupt status register value */
    registerValue = REG_READ32(unitBase + SADC_INT_STA_BASE);
    interruptBits =
        (uint8)((registerValue & SADC_INT_STA_SUB_FIFO_ALL) >> SADC_INT_STA_SUB_FIFO_WML_OFFSET((0u)));

    return interruptBits;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 9 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function get groupid.

 * \verbatim
 * Syntax             : static Adc_GroupType Adc_GetGrpIdThroughRcRchtIndex(
 *                                                            const Adc_GroupType startGrpId,
 *                                                            const Adc_RcRchtIndexType grpRcRchtIndex)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : startGrpId
                        grpRcRchtIndex

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function get groupid.
 * \endverbatim
 *******************************************************************************************************/
static Adc_GroupType Adc_GetGrpIdThroughRcRchtIndex(const Adc_GroupType startGrpId,
        const Adc_RcRchtIndexType grpRcRchtIndex)
{
    Adc_GroupType tempGrpId;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    if (ADC_RCHT_INDEX == coreHandlerPtr->globalConfigPtr->adcGroupCfgPtr[startGrpId].groupRcRchtIndex)
    {
        tempGrpId = startGrpId + (Adc_GroupType)grpRcRchtIndex;
    }
    else
    {
        tempGrpId = startGrpId + (Adc_GroupType)grpRcRchtIndex - 1U;
    }

    return tempGrpId;
}
/* fast code function 9 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 8 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function init buffer.

 * \verbatim
 * Syntax             : static void Adc_Ip_InitBuffer(Adc_ValueGroupType *buffer, uint8 bufferSize,
 *                                                    Adc_ValueGroupType initValue)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : buffer
                        bufferSize
                        initValue

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function init buffer.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_InitBuffer(Adc_ValueGroupType *buffer, uint8 bufferSize, Adc_ValueGroupType initValue)
{
    uint8 bufferIndex = 0U;

    for (; bufferIndex < bufferSize; bufferIndex++)
    {
        buffer[bufferIndex] = initValue;
    }

    return;
}
/* fast code function 8 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 12 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief disable trigger and disconnect fifo.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_TriggerDisable(
 *                                              const Adc_RegisterBaseType ipHardwareUnitbase,
 *                                              Adc_GroupType disableGrpId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : ipHardwareUnitbase
                        disableGrpId

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : disable trigger and disconnect fifo.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_TriggerDisable(const Adc_RegisterBaseType ipHardwareUnitbase,
        Adc_GroupType disableGrpId)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    const Adc_GroupConfigType *tempGrpCfg = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[disableGrpId];
    Adc_ErrorIdType dmaDisableStatus = 0U;
    uint8 rcRchtIdx = (uint8)tempGrpCfg->groupRcRchtIndex;
    /* rcht&rc0 share same subfifo, rc1/2/3 use independent sub_fifo1/2/3 */
    uint8 subFifoSel = (rcRchtIdx == 0u) ? rcRchtIdx : (rcRchtIdx - 1u);
    /* interrupt sta en */
    uint32 staEnVal;
    /* interrupt sta en register val */
    uint32 staEnReg;
    /* sig_en register set loop */
    uint8 sigEnLoop = 0;
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_05();
    coreHandlerPtr->allGrpInfo[disableGrpId].groupConvStatus = ADC_ALREADY_FINISHED_CONVERTED;

    /* exit critical zone */
    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_05();

    if (ADC_INTERRUPT_MODE == tempGrpCfg->groupTransferType)
    {
        /* config adc subfifo0 disconnected to used RCx/RCHT */
        Adc_WriteRegister((ipHardwareUnitbase + SADC_SUB_FIFO_BASE((uint32)ADC_SUBFIFO_ID(subFifoSel))),
                          SADC_SUB_FIFO_SUB_RC_EN_FIELD_OFFSET,
                          SADC_SUB_FIFO_SUB_RC_EN_FIELD_SIZE,
                          ADC_BIT_DISABLE << (4U - rcRchtIdx));
        /* disable adc fifo watermark interrupt */
        /* disable fifo watermark int signal */
        Adc_WriteRegister((ipHardwareUnitbase + SADC_INT_SIG_EN_BASE),
                          SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET((subFifoSel)),
                          SADC_INT_SIG_EN_SUB_FIFO_SINGLE_FIELD_SIZE, ADC_BIT_DISABLE);
        /* disable fifo watermark int status */
        Adc_WriteRegister((ipHardwareUnitbase + SADC_INT_STA_EN_BASE),
                          SADC_INT_STA_EN_SUB_FIFO_WML_OFFSET((subFifoSel)),
                          SADC_INT_STA_EN_SUB_FIFO_SINGLE_FIELD_SIZE, ADC_BIT_DISABLE);
        staEnReg = (REG_READ32(ipHardwareUnitbase + SADC_INT_STA_EN_BASE) & SADC_INT_STA_EN_SUB_FIFO_ALL);
        staEnVal = staEnReg >> SADC_INT_STA_EN_SUB_FIFO_WML_OFFSET((0u));
        for(; sigEnLoop < ADC_SUBFIFO_CNT; sigEnLoop++)
        {
            /* 0x8: check if the highest bit in sub fifo is 1 */
            if (((staEnVal << sigEnLoop) & 0x8UL) != 0UL)
            {
                /* Interrupts are guaranteed to be triggered by the lowest-priority rc/rcht */
                REG_WRITE32(0x1UL << SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET((3U - sigEnLoop)),
                                                            ipHardwareUnitbase + SADC_INT_SIG_EN_BASE);
                break;
            }
        }


    } /* else not neededed */

#if (ADC_DMA_SUPPORTED == STD_ON) /* AdcEnableDmaTransferMode enabled */
    else
    {
        if (ADC_E_DMA_STOP_FAIL == Adc_Ip_StopDmaTransmission(disableGrpId))
        {
            dmaDisableStatus = ADC_E_DMA_STOP_FAIL;
        } /* else not needed */
    }

#endif /* AdcEnableDmaTransferMode enabled */
    return dmaDisableStatus;
}
/* fast code function 12 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 15 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief enable trigger.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_TriggerDisable(
 *                                                      const Adc_RegisterBaseType ipHardwareUnitbase,
 *                                                      Adc_GroupType disableGrpId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : ipHardwareUnitbase
                        enableGrpId

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : enable trigger.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_TriggerEnable(const Adc_RegisterBaseType ipHardwareUnitbase,
        Adc_GroupType enableGrpId)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    const Adc_GroupConfigType *tempGrpCfg = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[enableGrpId];
    Adc_ErrorIdType dmaStartStatus = 0U;
    uint8 rcRchtIdx = (uint8)tempGrpCfg->groupRcRchtIndex;
    /* sw rc uint index */
    uint8 rcIdx = rcRchtIdx - 1U;
    /* rcht&rc0 share same subfifo, rc1/2/3 use independent sub_fifo1/2/3 */
    uint8 subFifoSel = (rcRchtIdx == 0u) ? rcRchtIdx : (rcRchtIdx - 1u);
    /* interrupt sig en register val */
    uint32 sigEnVal;
    /* rc status */
    uint32 rcSta;

    if (ADC_INTERRUPT_MODE == tempGrpCfg->groupTransferType)
    {
        /* get the sig_en value */
        sigEnVal = REG_READ32(ipHardwareUnitbase + SADC_INT_SIG_EN_BASE) & SADC_INT_SIG_EN_SUB_FIFO_ALL;
        /* Config adc subfifo0 disconnected to used RCx/RCHT */
        Adc_WriteRegister((ipHardwareUnitbase + SADC_SUB_FIFO_BASE((uint32)ADC_SUBFIFO_ID(subFifoSel))),
                          SADC_SUB_FIFO_SUB_RC_EN_FIELD_OFFSET,
                          SADC_SUB_FIFO_SUB_RC_EN_FIELD_SIZE,
                          ADC_BIT_ENABLE << (4U - rcRchtIdx));
        Adc_WriteRegister((ipHardwareUnitbase + SADC_INT_STA_EN_BASE),
                          SADC_INT_STA_EN_SUB_FIFO_WML_OFFSET(subFifoSel),
                          SADC_INT_STA_EN_SUB_FIFO_SINGLE_FIELD_SIZE, ADC_BIT_ENABLE);
        if ((0x1UL << SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET(subFifoSel)) > sigEnVal)
        {
            /* Interrupts are guaranteed to be triggered by the lowest-priority rc/rcht */
            REG_WRITE32(0x1UL << SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET(subFifoSel),
                                                            ipHardwareUnitbase + SADC_INT_SIG_EN_BASE);
        }
    }

#if (ADC_DMA_SUPPORTED == STD_ON) /* AdcEnableDmaTransferMode enabled */
    else
    {
        if (ADC_E_DMA_START_FAIL == Adc_Ip_StartDmaTransmission(enableGrpId))
        {
            dmaStartStatus = ADC_E_DMA_START_FAIL;
        } /* else not needed */
    }

#endif /* AdcEnableDmaTransferMode enabled */

#if (ADC_DMA_SUPPORTED == STD_ON)

    if (ADC_E_DMA_START_FAIL != dmaStartStatus)
    {
#endif /* #if (ADC_DMA_SUPPORTED == STD_ON) */

        /* enter critical zone */
        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_06();

        if (ADC_TRIGG_SRC_SW == tempGrpCfg->triggerSource)
        {
            /* ready to set current pointer to 0 */
            Adc_WriteRegister((ipHardwareUnitbase + SADC_RC_BASE((uint32)rcIdx)),
                              SADC_RC_SOFT_OVWR_POINT_EN_FIELD_OFFSET,
                              SADC_RC_SOFT_OVWR_POINT_EN_FIELD_SIZE,
                              ADC_BIT_ENABLE);
            /* set current pointer to 0. */
            Adc_WriteRegister((ipHardwareUnitbase + SADC_RC_BASE((uint32)rcIdx)),
                              SADC_RC_CUR_POINT_FIELD_OFFSET,
                              SADC_RC_CUR_POINT_FIELD_SIZE,
                              ADC_BIT_DISABLE);

            rcSta = REG_READ32(ipHardwareUnitbase + SADC_RC_BASE((uint32)rcIdx));
            if ((rcSta >> SADC_RC_SOFT_TRG_DONE_STATUS_FIELD_OFFSET) == ADC_BIT_DISABLE)
            {
                dmaStartStatus = ADC_E_SW_TRIG_NOT_READY;
            }
            else
            {
                /* enable rc software trigger */
                Adc_WriteRegister((ipHardwareUnitbase + SADC_RC_BASE((uint32)rcIdx)),
                                  SADC_RC_SOFT_TRG_FIELD_OFFSET,
                                  SADC_RC_SOFT_TRG_FIELD_SIZE,
                                  ADC_BIT_ENABLE);
                coreHandlerPtr->allGrpInfo[enableGrpId].groupConvStatus = ADC_NOT_YET_FINISHED_CONVERTED;
            }


        }
        /* hw trigger mode */
        else
        {
            coreHandlerPtr->allGrpInfo[enableGrpId].groupConvStatus = ADC_NOT_YET_FINISHED_CONVERTED;
        }

        /* exit critical zone*/
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_06();

#if (ADC_DMA_SUPPORTED == STD_ON)
    } /* else not needed */

#endif /* #if (ADC_DMA_SUPPORTED == STD_ON) */

    return dmaStartStatus;
}
/* fast code function 15 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 5 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief check if channel result and config match.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_CheckValueMatch(Adc_ValueGroupType conversionValue,
                            const Adc_GroupConfigType *grpCfg, Adc_ValueGroupType *intBuffer,
                            Adc_ValueGroupType *cvtFlag)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : conversionValue
                        grpCfg
                        intBuffer
						cvtFlag

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : check if channel result and config match.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_CheckValueMatch(Adc_ValueGroupType conversionValue,
        const Adc_GroupConfigType *grpCfg, Adc_ValueGroupType *intBuffer, Adc_ValueGroupType *cvtFlag)
{
    Adc_ChannelType chnIndex = 0U;
    Adc_ErrorIdType errValueStauts = 0U;
    /* Adc physical id calculation formula is physical id =
    (physical id value configured in the register * 2) */
    /* if channel is P end,The physical id must be increased by 1 extra */
    /* 0x7: physical id value bit width */
    Adc_ChannelType chnlPhysicalId = (Adc_ChannelType)(
            (((conversionValue) >>ADC_CHNL_PHYSICAL_ID_START_BIT_IN_CONV_VALUE) & 0x7UL) * 2UL);
    /* 0x7: mux id value bit width */
    uint32 chnlMuxId = (conversionValue >> ADC_CHNL_MUX_ID_START_BIT_IN_CONV_VALUE) & 0x7UL;

    if (ADC_BIT_ENABLE == ((conversionValue >> ADC_CHNL_END_START_BIT_IN_CONV_VALUE) & ADC_BIT_ENABLE))
    {
        /* 1:P end 0:N end */
        chnlPhysicalId = chnlPhysicalId + 1U;
    } /* else not needed */

    for (; chnIndex < grpCfg->channelCount; chnIndex++)
    {
        if (chnlPhysicalId == grpCfg->groupChannelCfgPtr[chnIndex].physicalChannelId)
        {
            if ((chnlMuxId == (uint32)grpCfg->groupChannelCfgPtr[chnIndex].channelMuxId) &&
                (FALSE == cvtFlag[grpCfg->groupChannelCfgPtr[chnIndex].logicalChannelId]))
            {
                /* 0xFFF: convert value bit width */
                intBuffer[grpCfg->groupChannelCfgPtr[chnIndex].logicalChannelId] = (conversionValue & 0xFFFUL);
                cvtFlag[grpCfg->groupChannelCfgPtr[chnIndex].logicalChannelId] = TRUE;
                break;
            } /* else not needed */
        } /* else not needed */
    }

    AdcFaultInj_Adc_CheckValueMatchFail();
    if (chnIndex > ADC_USED_MAX_GROUP_CHNL_COUNT)
    {
        errValueStauts = ADC_E_VALUE_MATCH;
    } /* else not needed */

    return errValueStauts;
}
/* fast code function 5 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"


#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief read fifo.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_ReadFifo(const Adc_RegisterBaseType unitBase, Adc_GroupType grpId,
                                       Adc_ValueGroupType *buffer, Adc_ValueGroupType *flag)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : unitBase
                        grpId
                        buffer
                        flag

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : read fifo.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_ReadFifo(const Adc_RegisterBaseType unitBase, Adc_GroupType grpId,
                                       Adc_ValueGroupType *buffer, Adc_ValueGroupType *flag)
{
    Adc_ChannelType chnlIndex = 0U;
    Adc_ValueGroupType tempValue;
    Adc_ErrorIdType errorValueStatus = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    const Adc_GroupConfigType *tempGrpCfg = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[grpId];
    /* rc/rcht select */
    uint8 rcRchtIdx = (uint8)tempGrpCfg->groupRcRchtIndex;
    /* rcht&rc0 share same subfifo, rc1/2/3 use independent sub_fifo1/2/3 */
    uint8 subFifoSel = (rcRchtIdx == 0u) ? rcRchtIdx : (rcRchtIdx - 1u);


    for (; chnlIndex < tempGrpCfg->channelCount; chnlIndex++)
    {
        tempValue = REG_READ32(unitBase + SADC_SUB_FIFO_DATA_BASE(ADC_SUBFIFO_ID((uint32)subFifoSel)));

        if (ADC_E_VALUE_MATCH == Adc_CheckValueMatch(tempValue, tempGrpCfg, buffer, flag))
        {
            errorValueStatus = ADC_E_VALUE_MATCH;
            break;
        } /* else not needed */
    }
    return errorValueStatus;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"


/* normal code start */
#define ADC_START_SEC_CODE
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function config rcht entry.

 * \verbatim
 * Syntax             : static void Adc_Ip_ConfigRchtEntry(Adc_RegisterBaseType unitBase,
                                   const Adc_GroupConfigType *rchtGroupCfgPtr)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : unitBase
                        rchtGroupCfgPtr

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function config rcht entry.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_ConfigRchtEntry(Adc_RegisterBaseType unitBase,
                                   const Adc_GroupConfigType *rchtGroupCfgPtr)
{
    uint32 logChanId;
    uint32 phyChanId;
    Adc_ChannelType rchtChannelIndex = 0U;
    const Adc_ChannelConfigType *rchtChannelCfgPtr;

    for (; rchtChannelIndex < rchtGroupCfgPtr->channelCount; rchtChannelIndex++)
    {
        rchtChannelCfgPtr = &rchtGroupCfgPtr->groupChannelCfgPtr[rchtChannelIndex];
        logChanId = (uint32)rchtChannelCfgPtr->logicalChannelId;
        phyChanId = (uint32)rchtChannelCfgPtr->physicalChannelId;
        /* if group is hardware trigger source, config the RCHT entry */
        /* #10 config the channel negative or positive end */
        Adc_WriteRegister((unitBase + SADC_RCHT_ENTRY_BASE(logChanId)),
                          SADC_RCHT_ENTRY_CHNL_END_FIELD_OFFSET,
                          SADC_RCHT_ENTRY_CHNL_END_FIELD_SIZE,
                          (phyChanId % 2U));
        /* #20 config the channel physical id */
        /* physical id equals physical id in configuration divide by 2 */
        /* if channel with P end,physical id will plus 1 */
        /* if channel with N end,physical id won't plus 1 */
        Adc_WriteRegister((unitBase + SADC_RCHT_ENTRY_BASE(logChanId)),
                          SADC_RCHT_ENTRY_CONTROL_CHNL_FIELD_OFFSET,
                          SADC_RCHT_ENTRY_CONTROL_CHNL_FIELD_SIZE,
                          (phyChanId >> 1U));
        /* #30 config the channel mux id */
        Adc_WriteRegister((unitBase + SADC_RCHT_ENTRY_BASE(logChanId)),
                          SADC_RCHT_ENTRY_CHNL_MUXID_FIELD_OFFSET,
                          SADC_RCHT_ENTRY_CHNL_MUXID_FIELD_SIZE,
                          (rchtChannelCfgPtr->channelMuxId));
        /* #40 config the channel sample ctrl selection */
        Adc_WriteRegister((unitBase + SADC_RCHT_ENTRY_BASE(logChanId)),
                          SADC_RCHT_ENTRY_CSEL_FIELD_OFFSET, SADC_RCHT_ENTRY_CSEL_FIELD_SIZE,
                          rchtChannelCfgPtr->sampleClock);
    }

    return;
}

/********************************************************************************************************
 * \brief This function config rc entry.

 * \verbatim
 * Syntax             : static void Adc_Ip_ConfigRcEntry(Adc_RegisterBaseType unitBase,
                                 const Adc_GroupConfigType *rcGroupCfgPtr)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : unitBase
                        rcGroupCfgPtr

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function config rc entry.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_ConfigRcEntry(Adc_RegisterBaseType unitBase,
                                 const Adc_GroupConfigType *rcGroupCfgPtr)
{
    uint32 logChanId;
    const Adc_ChannelConfigType *rcChannelCfgPtr;
    Adc_ChannelType rcChannelIndex = 0U;
    /* rc uint index */
    uint32 rcIdx = (uint32)rcGroupCfgPtr->groupRcRchtIndex - 1U;



    for (; rcChannelIndex < rcGroupCfgPtr->channelCount; rcChannelIndex++)
    {
        rcChannelCfgPtr = &rcGroupCfgPtr->groupChannelCfgPtr[rcChannelIndex];
        logChanId = (uint32)rcChannelCfgPtr->logicalChannelId;
        /* if group is software trigger source, config the rc entry */
        /* #10 config the channel negative or positive end */
        Adc_WriteRegister((unitBase + SADC_RC_ENTRY_BASE((rcIdx), logChanId)),
                            SADC_RC_ENTRY_CHNL_END_FIELD_OFFSET,
                            SADC_RC_ENTRY_CHNL_END_FIELD_SIZE,
                            ((uint32)rcChannelCfgPtr->physicalChannelId % 2U));
        /* #20 config the channel physical id */
        /* physical id equals physical id in configuration divide by 2 */
        /* if channel with P end,physical id will plus 1 */
        /* if channel with N end,physical id won't plus 1 */
        Adc_WriteRegister((unitBase + SADC_RC_ENTRY_BASE((rcIdx), logChanId)),
                            SADC_RC_ENTRY_CONTROL_CHNL_FIELD_OFFSET,
                            SADC_RC_ENTRY_CONTROL_CHNL_FIELD_SIZE,
                            ((uint32)rcChannelCfgPtr->physicalChannelId >> 1U));
        /* #30 config the channel mux id */
        Adc_WriteRegister((unitBase + SADC_RC_ENTRY_BASE((rcIdx), logChanId)),
                            SADC_RC_ENTRY_CHNL_MUXID_FIELD_OFFSET,
                            SADC_RC_ENTRY_CHNL_MUXID_FIELD_SIZE,
                            (rcChannelCfgPtr->channelMuxId));
        /* #40 config the channel sample ctrl selection */
        Adc_WriteRegister((unitBase + SADC_RC_ENTRY_BASE((rcIdx), logChanId)),
                            SADC_RC_ENTRY_CSEL_FIELD_OFFSET,
                            SADC_RC_ENTRY_CSEL_FIELD_SIZE,
                            rcChannelCfgPtr->sampleClock);
    }

    return;
}

/********************************************************************************************************
 * \brief config goup config.

 * \verbatim
 * Syntax             : static void Adc_Ip_ConfigGroup(const Adc_ConfigType *adcConfigPtr, Adc_HwUnitType hwUnitIndex)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcConfigPtr
                        hwUnitIndex

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : config goup config.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_ConfigGroup(const Adc_ConfigType *adcConfigPtr, Adc_HwUnitType hwUnitIndex)
{
    /* rc uint index */
    uint32 rcIdx;
    /* group index */
    Adc_GroupType groupIndex = 0U;
    /* adc unit base address */
    Adc_RegisterBaseType base =
        Adc_BaseAddress[adcConfigPtr->adcUnitCfgPtr[hwUnitIndex].hwModulePhysicalId];
    /* ipGroupId of the first group in the unit */
    Adc_GroupType startGroupId = adcConfigPtr->adcUnitCfgPtr[hwUnitIndex].startGroupIdInUnit;
    /* adc group configuration */
    const Adc_GroupConfigType *groupCfgPtr = &adcConfigPtr->adcGroupCfgPtr[startGroupId];


    /* group trigger source is hardware trigger source */
    if (ADC_TRIGG_SRC_HW == groupCfgPtr->triggerSource)
    {
        /* #10 config rcht entries */
        Adc_Ip_ConfigRchtEntry(base, groupCfgPtr);
        groupIndex++;
#if (ADC_DMA_SUPPORTED == STD_ON)

        if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
        {
            /* #20 config dma enabled for rcht */
            Adc_WriteRegister((base + SADC_DMA_BASE), SADC_DMA_RCHT_CONVERSION_DONE_FIELD_OFFSET,
                              SADC_DMA_RCHT_CONVERSION_DONE_FIELD_SIZE, ADC_BIT_DISABLE);
            Adc_WriteRegister((base + SADC_DMA_BASE), SADC_DMA_CHN0_RCHT_ENABLE_FIELD_OFFSET,
                              SADC_DMA_CHN0_RCHT_ENABLE_FIELD_SIZE, ADC_BIT_ENABLE);
        } /* else not needed */

#endif
    } /* else not needed */

    for (; groupIndex < adcConfigPtr->adcUnitCfgPtr[hwUnitIndex].groupCountPerUnit; groupIndex++)
    {
        groupCfgPtr = &adcConfigPtr->adcGroupCfgPtr[startGroupId + groupIndex];
        rcIdx = (uint32)groupCfgPtr->groupRcRchtIndex - 1UL;
#if (ADC_DMA_SUPPORTED == STD_ON)

        if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
        {
            /* #30 config dma enabled for rc each conversion */
            Adc_WriteRegister((base + SADC_DMA_BASE),
                              (SADC_DMA_RC0_CONVERSION_DONE_FIELD_OFFSET - ((uint8)rcIdx)),
                              SADC_DMA_EACH_RHCT_RC_CONVERSION_DONE_FIELD_SIZE, ADC_BIT_DISABLE);

            /* 40 check which dma channel should be allocated */
            if (ADC_DMA_CHNL0 == groupCfgPtr->groupDmaChannelIndex)
            {
                /* allocate dma channel_0 to target rc */
                Adc_WriteRegister((base + SADC_DMA_BASE),
                                  (SADC_DMA_CHN0_RC0_ENABLE_FIELD_OFFSET - ((uint8)rcIdx)),
                                  SADC_DMA_CHN0_EACH_RCHT_RC_FIELD_SIEZ, ADC_BIT_ENABLE);
            }
            /* dma channel0 is used for ohter rcht/rc */
            else if (ADC_DMA_CHNL1 == groupCfgPtr->groupDmaChannelIndex)
            {
                /* allocate dma channel_1 to target rc */
                Adc_WriteRegister((base + SADC_DMA_BASE),
                                  (SADC_DMA_CHN1_RC0_ENABLE_FIELD_OFFSET - ((uint8)rcIdx)),
                                  SADC_DMA_CHN1_EACH_RCHT_RC_FIELD_SIEZ, ADC_BIT_ENABLE);
            }
            else
            {
                /* do nothing */
            }
        } /* else not needed */

#endif
        /* #50 config rc entries */
        Adc_Ip_ConfigRcEntry(base, groupCfgPtr);

        /* #60 choose software trigger moed to produce trigger signal */
        Adc_WriteRegister((base + SADC_RC_BASE((rcIdx))), SADC_RC_TRG_MODE_FIELD_OFFSET,
                          SADC_RC_TRG_MODE_FIELD_SIZE,  ADC_EACH_RC_SOFT_TRG_MODE);
        /* #70 ready to clear cur_pointer */
        Adc_WriteRegister((base + SADC_RC_BASE((rcIdx))), SADC_RC_SOFT_OVWR_POINT_EN_FIELD_OFFSET,
                          SADC_RC_SOFT_OVWR_POINT_EN_FIELD_SIZE, ADC_BIT_ENABLE);
        /* #80 cur_pointer is set to 0. */
        Adc_WriteRegister((base + SADC_RC_BASE((rcIdx))), SADC_RC_CUR_POINT_FIELD_OFFSET,
                          SADC_RC_CUR_POINT_FIELD_SIZE, 0U);
        /* #90 qStart is set to 0 */
        Adc_WriteRegister((base + SADC_RC_BASE((rcIdx))), SADC_RC_QSTART_FIELD_OFFSET,
                          SADC_RC_QSTART_FIELD_SIZE, 0U);
        /* #100 qEnd is set to channel count minus 1 */
        Adc_WriteRegister((base + SADC_RC_BASE((rcIdx))), SADC_RC_QEND_FIELD_OFFSET,
                          SADC_RC_QEND_FIELD_SIZE, ((uint32)groupCfgPtr->channelCount - 1U));


#if (ADC_DMA_SUPPORTED == STD_ON)

        if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
        {
            if (NULL_PTR != groupCfgPtr->notificationPtr)
            {
                /* cfg one trig set will trigger how many channels for dma mode */
                Adc_WriteRegister((base + SADC_RC_BASE((rcIdx))), SADC_RC_SOFT_TRG_TIMES_FIELD_OFFSET,
                                  SADC_RC_SOFT_TRG_TIMES_FIELD_SIZE, (uint32)groupCfgPtr->channelCount);
            }
            else
            {
                /* choose rc timmer trigger mode to produce trigger signal */
                Adc_WriteRegister((base + SADC_RC_BASE((rcIdx))), SADC_RC_TRG_MODE_FIELD_OFFSET,
                                    SADC_RC_TRG_MODE_FIELD_SIZE,  ADC_EACH_RC_TIMMER_TRG_MODE);
                /* config rc timer compare value 1 */
                Adc_WriteRegister((base + SADC_RC_TIMER_BASE((rcIdx))),
                                    SADC_RC_TIMER_CMP_VALUE_FIELD_OFFSET,
                                    SADC_RC_TIMER_CMP_VALUE_FIELD_SIZE, 1U);
                /* #config rc timer terminal value according to EB config */
                Adc_WriteRegister((base + SADC_RC_TIMER_BASE((rcIdx))),
                                    SADC_RC_TIMER_TMN_VALUE_FIELD_SIZE,
                                    SADC_RC_TIMER_TMN_VALUE_FIELD_OFFSET,
                                    (uint32)groupCfgPtr->groupSoftwareTriggerFreq);
            }
        }
        else
#endif /* #if (ADC_DMA_SUPPORTED == STD_ON) */
        {
            /* cfg one trig set will trigger how many channels */
            Adc_WriteRegister((base + SADC_RC_BASE((rcIdx))),
                                SADC_RC_SOFT_TRG_TIMES_FIELD_OFFSET,
                                SADC_RC_SOFT_TRG_TIMES_FIELD_SIZE,
                                ((uint32)groupCfgPtr->channelCount - 1UL));
        }


    }

    return;
}

/********************************************************************************************************
 * \brief Adpa io select ctrl
 * \verbatim
 * Syntax             : static void Adc_Ip_ApdaCtrl(void)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : None

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : Adpa io select ctrl
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_ApdaCtrl(void)
{
    uint8 i;
    /* set safety_domain(one IO occupies one register) apda ctrl value */
    for (i = 0u; i < ADC_APDA_CTRL_SF_CNT; i++)
    {
        Adc_WriteRegister((ADC_ANALOG_CTRL_BASE + SADC_ANA_APDA_CTRL_SF_BASE((uint32)i)),
                           SADC_ANA_APDA_VAL_OFFSET,
                           SADC_ANA_APDA_VAL_BITS_FIELD_SIZE, SADC_ANA_APDA_SF_VALUE);
    }

    /* set lp_domain(8 IOs share one register) adpa ctrl value */
    for (i = 0u; i < ADC_APDA_CTRL_LP_CNT; i++)
    {   /* when i = 3, bit16 - bit31 reserved */
        REG_WRITE32(SADC_ANA_APDA_LP_VALUE, ADC_SCR_LP_BASE + SADC_ANA_APDA_CTRL_LP_BASE((uint32)i));
    }
}


/********************************************************************************************************
 * \brief load adc trim value.

 * \verbatim
 * Syntax             : static void Adc_Ip_TrimValue(void)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : None

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : load adc trim value.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_TrimValue(void)
{
    /* bgr33 ana trim value */
    uint32 anaTrim;
    /* get rom trim status */
    /* bit12-bit17: vref_trim value, bit23: rom_trim_en*/
    uint32 romTrimStatus = REG_READ32(APBMUX_EFUSEC_BASE + ADC_ROM_TRIM_CFG_BASE);
    AdcFaultInj_Adc_Ip_TrimValueTrue();
    if ((ADC_ROM_TRIM_EN & romTrimStatus) != 0UL)
    {
        anaTrim = ((romTrimStatus >> 12U) & 0x3FUL);
        Adc_WriteRegister((ADC_ANALOG_CTRL_BASE + SADC_ANA_TIRM_CTRL_BASE),
                      SADC_ANA_TIRM_VREF_OFFSET,
                      SADC_ANA_TIRM_VREF_BITS_FIELD_SIZE, anaTrim);
        /* temperature coefficient: This value will be provided by the soc team before CS phase */
        Adc_WriteRegister((ADC_ANALOG_CTRL_BASE + SADC_ANA_TIRM_CTRL_BASE),
                      SADC_ANA_TC_VAL_OFFSET,
                      SADC_ANA_TC_VAL_BITS_FIELD_SIZE, ADC_TC_TRIM_VAL);
        /* enable the trim ctrl */
        Adc_WriteRegister((ADC_ANALOG_CTRL_BASE + SADC_ANA_TIRM_CTRL_BASE),
                      SADC_ANA_TIRM_EN_OFFSET,
                      SADC_ANA_TIRM_EN_BITS_FIELD_SIZE, ADC_BIT_ENABLE);
    }

}

/********************************************************************************************************
 * \brief Adc rstgen config.

 * \verbatim
 * Syntax             : static void Adc_Ip_RstGenConfig(Adc_HwUnitType adcIndex, uint8 rstCtrl)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcIndex - Adc Index
                        rstCtrl - rstgen Control

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : Adc rstgen config.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_RstGenConfig(Adc_HwUnitType adcIndex, uint8 rstCtrl)
{
    /* rstgen config */
    Adc_RegisterValue rstGenCfg = REG_READ32(ADC_RSTGEN_CTRL_BASE + ADC_RSTGEN_ADC_RESET((uint32)adcIndex));
    /* polling time counter */
    Adc_ValueGroupType pollingCnt = 0UL;
    AdcFaultInj_Adc_RstGenError();
    if (rstCtrl == ADC_RSTGEN_ADC_RESET_ASSERT)
    {
        rstGenCfg &= ~(0x1UL << ADC_RSTGEN_ADC_RESET_OFFSET);
        REG_WRITE32(rstGenCfg, ADC_RSTGEN_CTRL_BASE + ADC_RSTGEN_ADC_RESET((uint32)adcIndex));
        rstGenCfg = REG_READ32(ADC_RSTGEN_CTRL_BASE + ADC_RSTGEN_ADC_RESET((uint32)adcIndex));
		AdcFaultInj_Adc_LoopPollingError();
        /* wait for assert works */
        /* PRQA S 4558 3 */
        while((rstGenCfg & (0x1UL << ADC_RSTGEN_ADC_RESET_STA_OFFSET)) &&
                                                        (pollingCnt < ADC_POLLING_TIMEOUT_VALUE))
        {
            pollingCnt++;
            rstGenCfg = REG_READ32(ADC_RSTGEN_CTRL_BASE + ADC_RSTGEN_ADC_RESET((uint32)adcIndex));
        }
    }
    else if (rstCtrl == ADC_RSTGEN_ADC_RESET_DEASSERT)
    {
        rstGenCfg |= (0x1UL << ADC_RSTGEN_ADC_RESET_OFFSET);
        REG_WRITE32(rstGenCfg, ADC_RSTGEN_CTRL_BASE + ADC_RSTGEN_ADC_RESET((uint32)adcIndex));
        rstGenCfg = REG_READ32(ADC_RSTGEN_CTRL_BASE + ADC_RSTGEN_ADC_RESET((uint32)adcIndex));
		AdcFaultInj_Adc_LoopPollingError();
        /* wait for deassert works */
        /* PRQA S 4558 3 */
        while((!(rstGenCfg & (0x1UL << ADC_RSTGEN_ADC_RESET_STA_OFFSET))) &&
                                                        (pollingCnt < ADC_POLLING_TIMEOUT_VALUE))
        {
            pollingCnt++;
            rstGenCfg = REG_READ32(ADC_RSTGEN_CTRL_BASE + ADC_RSTGEN_ADC_RESET((uint32)adcIndex));
        }
    }
    else
    {
        /* do nothing avoid warning */
    }
}

/********************************************************************************************************
 * \brief Adc ckhen config.

 * \verbatim
 * Syntax             : static void Adc_Ip_CkGenConfig(Adc_HwUnitType adcIndex, uint8 ckGenCtrl)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcIndex - Adc Index
                        ckGenCtrl - ckgen Control

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : Adc ckgen config.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_CkGenConfig(Adc_HwUnitType adcIndex, uint8 ckGenCtrl)
{
    /* rstgen config */
    Adc_RegisterValue clkGateSet = REG_READ32(ADC_CKGEN_CTRL_BASE + ADC_CKGEN_ADC_CLOCK_GATE((uint32)adcIndex));
    /* polling time counter */
    Adc_ValueGroupType pollingCnt = 0UL;
    AdcFaultInj_Adc_CkGenError();
    if (ckGenCtrl == ADC_CKGEN_ADC_CLOCK_GATING)
    {
        clkGateSet &= ~(0x1UL << ADC_CKGEN_ADC_CLOCK_GATE_OFFSET);
        REG_WRITE32(clkGateSet, ADC_CKGEN_CTRL_BASE + ADC_CKGEN_ADC_CLOCK_GATE((uint32)adcIndex));
        clkGateSet = REG_READ32(ADC_CKGEN_CTRL_BASE + ADC_CKGEN_ADC_CLOCK_GATE((uint32)adcIndex));
		AdcFaultInj_Adc_LoopPollingError();
		
        /* wait for clk gate set works */
        /* PRQA S 4558 3 */
        while((!(clkGateSet & (0x1UL << ADC_CKGEN_ADC_CLOCK_GATE_STA_OFFSET))) &&
                                                        (pollingCnt < ADC_POLLING_TIMEOUT_VALUE))
        {
            pollingCnt++;
            clkGateSet = REG_READ32(ADC_CKGEN_CTRL_BASE + ADC_CKGEN_ADC_CLOCK_GATE((uint32)adcIndex));
        }
    }
    else if (ckGenCtrl == ADC_CKGEN_ADC_CLOCK_UNGATING)
    {
        clkGateSet = REG_READ32(ADC_CKGEN_CTRL_BASE + ADC_CKGEN_ADC_CLOCK_GATE((uint32)adcIndex));
        clkGateSet |= (0x1UL << ADC_CKGEN_ADC_CLOCK_GATE_OFFSET);
        REG_WRITE32(clkGateSet, ADC_CKGEN_CTRL_BASE + ADC_CKGEN_ADC_CLOCK_GATE((uint32)adcIndex));
        clkGateSet = REG_READ32(ADC_CKGEN_CTRL_BASE + ADC_CKGEN_ADC_CLOCK_GATE((uint32)adcIndex));
		AdcFaultInj_Adc_LoopPollingError();
        /* wait for clk gate set works */
        /* PRQA S 4558 3 */
        while((clkGateSet & (0x1UL << ADC_CKGEN_ADC_CLOCK_GATE_STA_OFFSET)) &&
                                                                (pollingCnt < ADC_POLLING_TIMEOUT_VALUE))
        {
            pollingCnt++;
            clkGateSet = REG_READ32(ADC_CKGEN_CTRL_BASE + ADC_CKGEN_ADC_CLOCK_GATE((uint32)adcIndex));
        }
    }
    else
    {
        /* do nothing avoid warning */
    }
}

/********************************************************************************************************
 * \brief init the sync clock config.

 * \verbatim
 * Syntax             : static void Adc_Ip_SyncClkConfig(const Adc_ConfigType *adcIpCfgPtr,
 *                                                      Adc_ValueGroupType *syncClk, uint8 adcUnitCount)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcIpCfgPtr - Pointer to configuration set
                        syncClk - Pointer to sync clk set
                        adcUnitCount - unit count

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : init the sync clock config.
 * \endverbatim
 *******************************************************************************************************/
/* PRQA S 3673 3 */
static void Adc_Ip_SyncClkConfig(const Adc_ConfigType *adcIpCfgPtr, Adc_ValueGroupType *syncClk, uint8 adcUnitCount)
{
    /* adc unit base address */
    Adc_RegisterBaseType base;
    /* hardware Unit index */
    Adc_HwUnitType uintIndex;
    /* sync config select */
    Adc_RegisterValue syncSel = 0UL;
    /* clock register value */
    Adc_RegisterValue clkCfg;
    for (uintIndex = 0; uintIndex < adcUnitCount; uintIndex++)
    {
        /* 0xFF: adc which no need set sync clk */
        if (syncClk[uintIndex] != 0xFFUL)
        {
            /* rstgen assert */
            Adc_Ip_RstGenConfig((uint8)(syncClk[uintIndex]), ADC_RSTGEN_ADC_RESET_ASSERT);
        }
    }
    for (uintIndex = 0; uintIndex < adcUnitCount; uintIndex++)
    {
        /* 0xFF: adc which no need set sync clk */
        if (syncClk[uintIndex] != 0xFFUL)
        {
            /* ckgen set gate */
            Adc_Ip_CkGenConfig((uint8)(syncClk[uintIndex]), ADC_CKGEN_ADC_CLOCK_GATING);
            /* sync adc clock sel */
            syncSel |= (0x1UL << SADC_ANA_ADC_SYNC_SEL(syncClk[uintIndex]));
        }
    }
    /* sync clk enable */
    syncSel |= (0x1UL << SADC_ANA_ADC_SYNC_EN_OFFSET);
    /* configure Adc sync clk en */
    REG_WRITE32(syncSel, ADC_ANALOG_CTRL_BASE + SADC_ANA_ADC_SYNC_BASE);

    for (uintIndex = 0; uintIndex < adcUnitCount; uintIndex++)
    {
        /* 0xFF: adc which no need set sync clk */
        if (syncClk[uintIndex] != 0xFFUL)
        {
            /* rstgen deassert */
            Adc_Ip_RstGenConfig((uint8)(syncClk[uintIndex]), ADC_RSTGEN_ADC_RESET_DEASSERT);
        }
    }

    for (uintIndex = 0; uintIndex < adcUnitCount; uintIndex++)
    {
        /* 0xFF: adc which no need set sync clk */
        if (syncClk[uintIndex] != 0xFFUL)
        {
            base = Adc_BaseAddress[adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwModulePhysicalId];
            clkCfg =
                (((uint32)adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwClockSrcDivider - 1UL) <<
                SADC_CLK_CTRL_REF_LOW_FIELD_OFFSET) |
                (((uint32)adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwClockSrcDivider - 1UL) <<
                SADC_CLK_CTRL_REF_HIGH_FIELD_OFFSET);
            REG_WRITE32(clkCfg, base + SADC_CLK_CTRL_BASE);
        }
    }

    /* set adc1 clk ip gate */
    Adc_Ip_CkGenConfig(0u, ADC_CKGEN_ADC_CLOCK_UNGATING);
}


/********************************************************************************************************
 * \brief init the clock config.

 * \verbatim
 * Syntax             : static void Adc_Ip_ClkConfig(const Adc_ConfigType *adcIpCfgPtr)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcIpCfgPtr - Pointer to configuration set

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : init the clock config.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_ClkConfig(const Adc_ConfigType *adcIpCfgPtr)
{
    /* adc unit base address */
    Adc_RegisterBaseType base;
    /* hardware Unit index */
    Adc_HwModuleIndexType adcIndex;
    /* hardware Unit index */
    Adc_HwUnitType uintIndex = 0U;
    /* sync config select */
    Adc_RegisterValue syncSel;
    /* sync config flag */
    boolean syncFlag = FALSE;
    /* clock register value */
    Adc_RegisterValue clkCfg;
    /* sync clk buffer */
    Adc_ValueGroupType syncClkBuf[ADC_USED_UNIT_COUNT];
    /* init sync clk buffer */
    Adc_Ip_InitBuffer(syncClkBuf, ADC_USED_UNIT_COUNT, 0xFFUL);
    syncSel = REG_READ32(ADC_ANALOG_CTRL_BASE + SADC_ANA_ADC_SYNC_BASE);

    for (; uintIndex < adcIpCfgPtr->unitCount; uintIndex++)
    {
        adcIndex = adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwModulePhysicalId;
        base = Adc_BaseAddress[adcIndex];
        /* ADC1-6 support sync config */
        if (adcIndex != ADC_INDEX_ADC7)
        {
            if (adcIpCfgPtr->adcUnitCfgPtr[uintIndex].syncClk == TRUE)
            {
                if ((syncSel & (0x1UL << SADC_ANA_ADC_SYNC_EN_OFFSET)) != 0UL)
                {
                    /* sync config has been set by other core */
                    continue;
                }
                else
                {
                    syncFlag = TRUE;
                    syncClkBuf[uintIndex] = (Adc_ValueGroupType)adcIndex;
                }
            }
            else
            {
                /* config the adc not use sync config */
                if (adcIpCfgPtr->adcUnitCfgPtr[uintIndex].clk24Mused == TRUE)
                {
                    /* set clock bypass information */
                    clkCfg = 0x01UL;
                }
                else
                {
                    /* set in adc analog clk divider register */
                    clkCfg =
                        (((uint32)adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwClockSrcDivider - 1UL) <<
                        SADC_CLK_CTRL_REF_LOW_FIELD_OFFSET) |
                        (((uint32)adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwClockSrcDivider - 1UL) <<
                        SADC_CLK_CTRL_REF_HIGH_FIELD_OFFSET);
                }
                /* configure Adc analog part prescale value */
                REG_WRITE32(clkCfg, base + SADC_CLK_CTRL_BASE);
            }
        }
        else
        {
            /* adc7 not support suyn clk config */
            if (adcIpCfgPtr->adcUnitCfgPtr[uintIndex].clk24Mused == TRUE)
            {
                /* set clock bypass information */
                clkCfg = 0x01UL;
            }
            else
            {
                /* set in adc analog clk divider register */
                clkCfg =
                    (((uint32)adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwClockSrcDivider - 1UL) <<
                    SADC_CLK_CTRL_REF_LOW_FIELD_OFFSET) |
                    (((uint32)adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwClockSrcDivider - 1UL) <<
                    SADC_CLK_CTRL_REF_HIGH_FIELD_OFFSET);
            }
            /* configure Adc analog part prescale value */
            REG_WRITE32(clkCfg, base + SADC_CLK_CTRL_BASE);
        }
    }
    if (TRUE == syncFlag)
    {
        /* set sync clk config */
        Adc_Ip_SyncClkConfig(adcIpCfgPtr, syncClkBuf, ADC_USED_UNIT_COUNT);
    }
}

/********************************************************************************************************
 * \brief config hwunit config.

 * \verbatim
 * Syntax             : static void Adc_Ip_ConfigUnit(const Adc_ConfigType *adcConfigPtr, Adc_HwUnitType hwUnitIndex)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcConfigPtr
                        hwUnitIndex

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : config hwunit config.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_ConfigUnit(const Adc_ConfigType *adcConfigPtr, Adc_HwUnitType hwUnitIndex)
{
    /* adc unit base address */
    Adc_RegisterBaseType base =
        Adc_BaseAddress[adcConfigPtr->adcUnitCfgPtr[hwUnitIndex].hwModulePhysicalId];
    /* rc timmer Index */
    uint8 rcTimerIndex = 0U;
    /* fifo index */
    uint8 fifoIndex = 0U;
    /* monitor index */
    uint8 monitorIndex = 0U;
    /* temp reg value */
    uint32 temRegValue;

    /* #01 mask rdata unc err sta en */
    Adc_WriteRegister((base + SADC_FUSA_UNCOR_ERR_INT_STAT_EN), SADC_STA_EN_RDATA_UNC_ERR_FIELD_OFFSET,
                      SADC_STA_EN_RDATA_UNC_ERR_FIELD_SIZE, ADC_BIT_DISABLE);
    Adc_WriteRegister((base + SADC_FUSA_UNCOR_ERR_INT_STAT_EN),
                      SADC_STA_EN_DMA_EOBC_UNC_ERR_FIELD_OFFSET,
                      SADC_STA_EN_DMA_EOBC_UNC_ERR_FIELD_SIZE, ADC_BIT_DISABLE);
    /* #02 mask rdata unc err sig en */
    Adc_WriteRegister((base + SADC_FUSA_UNCOR_ERR_INT_SIG_EN), SADC_SIG_EN_RDATA_UNC_ERR_FIELD_OFFSET,
                      SADC_SIG_EN_RDATA_UNC_ERR_FIELD_SIZE, ADC_BIT_DISABLE);
    Adc_WriteRegister((base + SADC_FUSA_UNCOR_ERR_INT_SIG_EN),
                      SADC_SIG_EN_DMA_EOBC_UNC_ERR_FIELD_OFFSET,
                      SADC_SIG_EN_DMA_EOBC_UNC_ERR_FIELD_SIZE, ADC_BIT_DISABLE);
    /* #03 clear rdata unc err sta */
    temRegValue = REG_READ32(base + SADC_FUSA_UNCOR_ERR_INT_STAT);
    REG_WRITE32(temRegValue, (base + SADC_FUSA_UNCOR_ERR_INT_STAT));

    /* #10 config the HTC ready_len 0x1 */
    Adc_WriteRegister((base + SADC_HTC_BASE), SADC_HTC_READY_LEN_FIELD_OFFSET,
                      SADC_HTC_READY_LEN_FIELD_SIZE, 0x1U);
    /* #20 config the HTC done_len 0xF */
    Adc_WriteRegister((base + SADC_HTC_BASE), SADC_HTC_DONE_LEN_FIELD_OFFSET,
                      SADC_HTC_DONE_LEN_FIELD_SIZE, 0xFU);
    /* #30 config scheduler to master mode */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_MST_MODE_FIELD_OFFSET,
                      SADC_SCH_CFG_MST_MODE_FIELD_SIZE, ADC_SCHEDULER_MASTER_MODE);
    /* #40 config scheduler to async mode */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_SYNC_MODE_FIELD_OFFSET,
                      SADC_SCH_CFG_SYNC_MODE_FIELD_OFFSET, ADC_SCHEDULER_ASYNC_MODE);
    /* #50 config scheduler to enable the rotation */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_ROT_EN_FIELD_OFFSET,
                      SADC_SCH_CFG_ROT_EN_FIELD_SIZE, ADC_BIT_ENABLE);
    /* #60 reset timestamp */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_TS_RST_FIELD_OFFSET,
                      SADC_SCH_CFG_TS_RST_FIELD_SIZE, ADC_BIT_ENABLE);
    /* #70 release the reset of timestamp */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_TS_RST_FIELD_OFFSET,
                      SADC_SCH_CFG_TS_RST_FIELD_SIZE, ADC_BIT_DISABLE);

    /* #100 reset all RC timmers */
    for (; rcTimerIndex < ADC_RC_TIMER_CNT; rcTimerIndex++)
    {
        /* hold the reset. */
        Adc_WriteRegister((base + SADC_SOFT_RST_BASE),
                            (SADC_SOFT_RST_RC0_TMR_RST_FIELD_OFFSET + rcTimerIndex),
                            SADC_SOFT_RST_EACH_RC_TMR_RST_FIELD_SIZE, ADC_BIT_ENABLE);
        /* release the reset. */
        Adc_WriteRegister((base + SADC_SOFT_RST_BASE),
                            (SADC_SOFT_RST_RC0_TMR_RST_FIELD_OFFSET + rcTimerIndex),
                            SADC_SOFT_RST_EACH_RC_TMR_RST_FIELD_SIZE, ADC_BIT_DISABLE);
    }

    /* #110 config fifo packmode, 32bit mode */
    Adc_WriteRegister((base + SADC_FIFO_CFG_BASE),
                      SADC_FIFO_CFG_PACK_MODE_FIELD_OFFSET,
                      SADC_FIFO_CFG_PACK_MODE_FIELD_SIZE, ADC_FIFO_32BIT_MODE);

    /* #120 each Subfifo has 32 words depth */
    for (; fifoIndex < ADC_SUBFIFO_CNT; fifoIndex++)
    {
        Adc_WriteRegister((base + SADC_SUB_FIFO_BASE((uint32)fifoIndex)),
                        SADC_SUB_FIFO_SUB_START_FIELD_OFFSET,
                        SADC_SUB_FIFO_SUB_START_FIELD_SIZE, SADC_SUB_FIFO_SUB_START((uint32)fifoIndex));
    }

    /* #130 mask all monitor to choose the 0xFFF channel configuration */
    /* in this way, prevent sem errors */
    for (; monitorIndex < ADC_MONITOR_CNT; monitorIndex++)
    {
        Adc_WriteRegister((base + SADC_MNT_THRD_SINGLE_BASE((uint32)monitorIndex)),
                          SADC_MNT_THRD_SINGLE_HTHRD_FIELD_OFFSET,
                          SADC_MNT_THRD_SINGLE_HTHRD_FIELD_SIZE, ADC_MONITOR_FULL_MASK_VALUE);
    }

    Adc_WriteRegister((base + SADC_MNT_THRD_CONT_BASE),
                      SADC_MNT_THRD_CONT_HTHRD_FIELD_OFFSET,
                      SADC_MNT_THRD_CONT_HTHRD_FIELD_SIZE, ADC_MONITOR_FULL_MASK_VALUE);

    /* #140 mask sub-fifo3 overflow error interrupt */
    Adc_WriteRegister((base + SADC_COR_ERR_INT_STA_EN_BASE),
                      SADC_COR_ERR_INT_STA_EN_SUB3_OVF_FIELD_OFFSET,
                      SADC_COR_ERR_INT_STA_EN_SUB3_OVF_FIELD_SIZE, ADC_BIT_DISABLE);
    Adc_WriteRegister((base + SADC_COR_ERR_INT_SIG_EN_BASE),
                      SADC_COR_ERR_INT_SIG_EN_SUB3_OVF_FIELD_OFFSET,
                      SADC_COR_ERR_INT_SIG_EN_SUB3_OVF_FIELD_SIZE, ADC_BIT_DISABLE);
    Adc_WriteRegister((base + SADC_UNC_ERR_INT_STA_EN_BASE),
                      SADC_UNC_ERR_INT_STA_EN_SUB3_OVF_FIELD_OFFSET,
                      SADC_UNC_ERR_INT_STA_EN_SUB3_OVF_FIELD_SIZE, ADC_BIT_DISABLE);
    Adc_WriteRegister((base + SADC_UNC_ERR_INT_SIG_EN_BASE),
                      SADC_UNC_ERR_INT_SIG_EN_SUB3_OVF_FIELD_OFFSET,
                      SADC_UNC_ERR_INT_SIG_EN_SUB3_OVF_FIELD_SIZE, ADC_BIT_DISABLE);
    return;
}

/********************************************************************************************************
 * \brief config analog config.

 * \verbatim
 * Syntax             : static void Adc_Ip_ConfigAnalog(const Adc_ConfigType *adcConfigPtr, Adc_HwUnitType hwUnitIndex)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcConfigPtr
                        hwUnitIndex

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : config hwunit config.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_Ip_ConfigAnalog(const Adc_ConfigType *adcConfigPtr, Adc_HwUnitType hwUnitIndex)
{
    /* adc unit base address */
    Adc_RegisterBaseType base =
        Adc_BaseAddress[adcConfigPtr->adcUnitCfgPtr[hwUnitIndex].hwModulePhysicalId];
    /* uint analog register index */
    uint8 unitAnalogRegIndex = 0U;
    /* get ref voltage info */
    Adc_RefVoltageType refVol = adcConfigPtr->adcUnitCfgPtr[hwUnitIndex].refVoltageSelect;
    /* buf ctrl value */
    uint16 volBufCtrl;


    /* #10 check adc analog ref select according to selection */
    if ((ADC_INTERNAL_REF_3P3V == refVol) || (ADC_INTERNAL_REF_5V == refVol))
    {
        if (ADC_INTERNAL_REF_3P3V == refVol)
        {
            /* 0xFD02: 3.3v single end fixed ctrl values */
            volBufCtrl = SADC_ANA_BUF_CTRL_3V3_SINGLE_END_VALUE;
        }
        else
        {
            /* 0xFD42: 5v single end fixed ctrl values */
            volBufCtrl = SADC_ANA_BUF_CTRL_5V_SINGLE_END_VALUE;
        }

        for (; unitAnalogRegIndex < ADC_CONFIG_ANA_REG_CNT; unitAnalogRegIndex++)
        {
            /* #20 choose avdd to be the reference voltage */
            Adc_WriteRegister((base + SADC_ANA_PARA_BASE((uint32)unitAnalogRegIndex)),
                              SADC_ANA_PARA_REFSEL_FIELD_OFFSET,
                              SADC_ANA_PARA_REFSEL_FIELD_SIZE, ADC_VREFP1);
            /* #30 config sample control parameter */
            Adc_WriteRegister((base + SADC_ANA_PARA_BASE((uint32)unitAnalogRegIndex)),
                              SADC_ANA_PARA_SAMCTRL_FIELD_OFFSET,
                              SADC_ANA_PARA_SAMCTRL_FIELD_SIZE, unitAnalogRegIndex);
            /* set buf ctrl value to specific the voltage */
            Adc_WriteRegister((base + SADC_ANA_BUF_CTRL_BASE((uint32)unitAnalogRegIndex)),
                              SADC_ANA_BUF_CTRL_BITS_FIELD_OFFSET,
                              SADC_ANA_BUF_CTRL_BITS_FIELD_SIZE, volBufCtrl);
        }
    }
    else
    {
        for (; unitAnalogRegIndex < ADC_CONFIG_ANA_REG_CNT; unitAnalogRegIndex++)
        {
            /* #40 choose vref1/vref2 to be the reference voltage */
            Adc_WriteRegister((base + SADC_ANA_PARA_BASE((uint32)unitAnalogRegIndex)),
                              SADC_ANA_PARA_REFSEL_FIELD_OFFSET,
                              SADC_ANA_PARA_REFSEL_FIELD_SIZE, ADC_VREFP2);
            /* #50 config sample control parameter */
            Adc_WriteRegister((base + SADC_ANA_PARA_BASE((uint32)unitAnalogRegIndex)),
                              SADC_ANA_PARA_SAMCTRL_FIELD_OFFSET,
                              SADC_ANA_PARA_SAMCTRL_FIELD_SIZE, unitAnalogRegIndex);
        }
    }

    return;
}
/********************************************************************************************************
 * \brief This function does Adc reset operation.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_ConfigReset(
 *                          const Adc_ConfigType *adcConfigPtr,
 *                          Adc_HwUnitType hwUnitIndex)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcConfigPtr - Pointer to configuration set
 *                    : hwUnitIndex - Adc Unit logical index

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ipErrorStatus
 *                      ADC_NO_ERROR: No Error
 *                      ADC_E_INIT_FAIL: Init Failed

 * Description        : This function does Adc reset operation.
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_ConfigReset(const Adc_ConfigType *adcConfigPtr,
        Adc_HwUnitType hwUnitIndex)
{
    /* adc unit base address */
    Adc_RegisterBaseType base =
        Adc_BaseAddress[adcConfigPtr->adcUnitCfgPtr[hwUnitIndex].hwModulePhysicalId];
    /* the time of reading initial register */
    uint32 timeReadInitBit = 0UL;
    /* adc error */
    Adc_ErrorIdType ipErrorStatus;
    /* times for read register */
    uint8 readTime = 0U;
	/* initial status */
    uint32 initSTa;


    /* #10 disable all adc int signals */
    REG_WRITE32(SADC_INT_SIG_EN_ALL, base + SADC_INT_SIG_EN_BASE);
    /* #20 disable all adc int status */
    REG_WRITE32(SADC_INT_STA_EN_ALL, base + SADC_INT_STA_EN_BASE);
    /* #30 clear all adc int status */
    REG_WRITE32(SADC_INT_STA_ALL, base + SADC_INT_STA_BASE);

    /* #40 reset adc analog soft reset */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_ANA_RST_FIELD_OFFSET,
                      SADC_SOFT_RST_ANA_RST_FIELD_SIZE, ADC_BIT_DISABLE);
    /* #50 reset adc digital soft reset */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_DIG_RST_FIELD_OFFSET,
                      SADC_SOFT_RST_DIG_RST_FIELD_SIZE, ADC_BIT_ENABLE);
    /* analog gate config */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_ANA_CLK_FORCE_CG_FIELD_OFFSET,
                      SADC_SOFT_RST_ANA_CLK_FORCE_CG_FIELD_SIZE, ADC_BIT_ENABLE);

    /* #60 release adc analog soft reset */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_ANA_RST_FIELD_OFFSET,
                      SADC_SOFT_RST_ANA_RST_FIELD_SIZE, ADC_BIT_ENABLE);

    for (; readTime < 10U; readTime ++)
    {
        REG_READ32(base + SADC_SOFT_RST_BASE);
    }

    /* analog gate disable */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_ANA_CLK_FORCE_CG_FIELD_OFFSET,
                      SADC_SOFT_RST_ANA_CLK_FORCE_CG_FIELD_SIZE, ADC_BIT_DISABLE);

    /* #70 release adc digital soft reset */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_DIG_RST_FIELD_OFFSET,
                      SADC_SOFT_RST_DIG_RST_FIELD_SIZE, ADC_BIT_DISABLE);
    /* #80 config adc initialzation value */
    Adc_WriteRegister((base + SADC_INIT_BASE), SADC_INIT_VALUE_FIELD_OFFSET,
                      SADC_INIT_VALUE_FIELD_SIZE, ADC_INIT_INITVALUE_RESET_AND_CONFIG_VALUE);
    /* #90 set the adc initialization bit */
    Adc_WriteRegister((base + SADC_INIT_BASE), SADC_INIT_START_FIELD_OFFSET,
                      SADC_INIT_START_FIELD_SIZE, ADC_BIT_ENABLE);

    /* #100 wait initial adc done */
    for (; timeReadInitBit < ADC_POLLING_TIMEOUT_VALUE; timeReadInitBit++)
    {
        /* #130 check whether adc init done bit set */
        initSTa = REG_READ32(base + SADC_INIT_BASE);
        if (FALSE != (initSTa & (ADC_BIT_ENABLE << SADC_INIT_DONE_FIELD_OFFSET)))
        {
            break;
        } /* else not needed */
    }

    AdcFaultInj_Adc_Ip_ConfigResetFail();

    /* #120 check whether adc initialization timeout */
    if (timeReadInitBit >= ADC_POLLING_TIMEOUT_VALUE)
    {
        /* init time out */
        ipErrorStatus = ADC_E_INIT_FAIL;
    }
    else
    {
        /* init successfully */
        ipErrorStatus = ADC_NO_ERROR;
    }

    return ipErrorStatus;
}

#if (ADC_DMA_SUPPORTED == STD_ON) /* AdcEnableDmaTransferMode enbaled */
/********************************************************************************************************
 * \brief This function process dma data.

 * \verbatim
 * Syntax             : static void Adc_DmaDataProcess(Adc_RegisterBaseType HwUsedDmaBase,
 *                              Adc_GroupType dmaDataGroupId,const Adc_ValueGroupType *dmaBuffer,
 *                              const Adc_GroupConfigType *dmaDataGroupPtr)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : HwUsedDmaBase
                        dmaDataGroupId
                        dmaBuffer
                        dmaDataGroupPtr


 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function process dma data.
 * \endverbatim
 *******************************************************************************************************/
static void Adc_DmaDataProcess(Adc_RegisterBaseType HwUsedDmaBase, Adc_GroupType dmaDataGroupId,
                               const Adc_ValueGroupType *dmaBuffer,
                               const Adc_GroupConfigType *dmaDataGroupPtr)
{
    /* internal buffer */
    Adc_ValueGroupType interBuffer[ADC_USED_MAX_GROUP_CHNL_COUNT];
    /* converted flag buffer */
    Adc_ValueGroupType convFlag[ADC_USED_MAX_GROUP_CHNL_COUNT];
    /* channel index */
    Adc_ChannelType channelIndex = 0U;
    /* error number code */
    Adc_ErrorIdType dmaErrorStatus = 0U;
    /* temp value */
    const Adc_ValueGroupType *tempDmaBuffer = dmaBuffer;
    /* #10 init inter buffer with 0 */
    Adc_Ip_InitBuffer(interBuffer, ADC_USED_MAX_GROUP_CHNL_COUNT, 0x00UL);
    /* #10 init converted flag buffer with 0 */
    Adc_Ip_InitBuffer(convFlag, ADC_USED_MAX_GROUP_CHNL_COUNT, 0x00UL);
    /* #20 invalidate cache */
#if (ADC_NO_CACHEABLE_NEEDED == STD_OFF)
    /*PRQA S 0306  1*/
    (void)Mcal_InvalidateCache((uint32)tempDmaBuffer,
                        (((uint32)dmaDataGroupPtr->channelCount + 1U) * ADC_WORD_TO_BYTE));
#endif

    for (; channelIndex < dmaDataGroupPtr->channelCount; channelIndex++)
    {
            /* #30 check conversion values whether can match with group configuration
                   and sort them into internal buffer */
            if (ADC_E_VALUE_MATCH ==
                    Adc_CheckValueMatch(tempDmaBuffer[channelIndex + 1U], dmaDataGroupPtr, interBuffer, convFlag))
            {
                /* channel conversion value can not match group configuration */
                dmaErrorStatus = ADC_E_VALUE_MATCH;
                break;
            } /* else not needed */
    }
    if (ADC_E_VALUE_MATCH != dmaErrorStatus)
    {
        /* #40 handle next round group conversion */
        /* record errorId */
        dmaErrorStatus = Adc_Ip_ChnlValueHandle(HwUsedDmaBase, dmaDataGroupId,
                                                (const Adc_ValueGroupType *)interBuffer);
    } /* else not needed */

    /* to prevent dmaErrorStatus from no use*/
    /* PRQA S 3119  1 */
    ADC_DUMMY_STATEMENT(dmaErrorStatus);
    return;
}

/* PRQA S 3673  1 */
static void Adc_EndGroupConversionDma(Dma_ControllerStatusType dma_stat, void *context)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const* coreHandlerPtr = Adc_Handler[coreId];
    /* #10 dma disable status */
    Adc_ErrorIdType dmaStopStatus = 0U;
    /* #20 get group used dma channel configuration */
    /*PRQA S 0316  1*/
    const Dma_ChannelConfigType *chan = (const Dma_ChannelConfigType *)context;
    /* #30 get adc group configuration */
    /*PRQA S 0316  1*/
    const Adc_GroupConfigType *damGroupCfgPtr = (Adc_GroupConfigType *)chan->context;
    /* #40 get unit configuration the group belongs to */
    const Adc_HwUnitConfigType *dmaUnitCfgPtr =
        &(coreHandlerPtr->globalConfigPtr)->adcUnitCfgPtr[damGroupCfgPtr->belongUnitLogicalId];
    /* #50 group id */
    Adc_GroupType dmaGroupId = Adc_GetGrpIdThroughRcRchtIndex(dmaUnitCfgPtr->startGroupIdInUnit,
                               damGroupCfgPtr->groupRcRchtIndex);
    if (coreId != dmaUnitCfgPtr->coreAllocatedUint)
    {
        /* check the core generate the int is same as the configuration */
        dmaStopStatus = ADC_E_PARAM_CORE;
    }
    else
    {
        if (DMA_COMPLETED == dma_stat)
        {
            /* #60 check whether group is already stopped by
                Adc_StopGroupConversion/Adc_EnableHardwareTrigger */
            if (ADC_NOT_YET_FINISHED_CONVERTED == coreHandlerPtr->allGrpInfo[dmaGroupId].groupConvStatus)
            {
                /* #70 diable trigger */
                if (ADC_E_DMA_STOP_FAIL == Adc_Ip_TriggerDisable(Adc_BaseAddress[dmaUnitCfgPtr->hwModulePhysicalId],
                        dmaGroupId))
                {
                    /* dma stop failed */
                    dmaStopStatus = ADC_E_DMA_STOP_FAIL;
                }
                else
                {
                    /* #80 process dma conversion values */
                    Adc_DmaDataProcess(Adc_BaseAddress[dmaUnitCfgPtr->hwModulePhysicalId], dmaGroupId,
                        Adc_DmaBufAdcUnit[
                            ((uint8)dmaUnitCfgPtr->hwModulePhysicalId * ADC_DMA_PER_UNIT_CHNL_CNT) +
                            (uint8)damGroupCfgPtr->groupDmaChannelIndex], damGroupCfgPtr);
                }
            } /* else not needed */
        } /* else not needed */
    }
    /* prevent dmaStopStatus from no use */
    /* PRQA S 3119  1 */
    ADC_DUMMY_STATEMENT(dmaStopStatus);
}

/********************************************************************************************************
 * \brief config dma.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_ConfigDma(const Adc_ConfigType *adcConfigPtr,
                                        Adc_HwUnitType hwLogicalModuleId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcConfigPtr
                        hwLogicalModuleId

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : config dma.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_ConfigDma(const Adc_ConfigType *adcConfigPtr,
                                        Adc_HwUnitType hwLogicalModuleId)
{
    /* hardware unit configuration */
    const Adc_HwUnitConfigType *unitCfgPtr = &adcConfigPtr->adcUnitCfgPtr[hwLogicalModuleId];
    /* group index */
    Adc_GroupType groupIndex = 0U;
    /* the first group id in current unit */
    Adc_GroupType unitStartGroupId = unitCfgPtr->startGroupIdInUnit;
    /* group configuration */
    Adc_GroupConfigType *groupCfgPtr;
    /* dma channel allocation variable */
    Dma_InstanceConfigType dmaAdcConfigData;
    /* get dma channel status */
    uint8 dmaConfigRet;
    /* allocate dma channel status */
    Adc_ErrorIdType dmaCfgStatus = 0U;
    /* dma channel infomation */
    Dma_ChannelConfigType *chan;
    /* detailed dma channel configuration */
    Dma_DeviceConfigType dmaDetailCfg;
    /* adc dma mux id base */
    uint16 muxIdBase;
    /* adc dma index value */
    uint16 adcDmaIdx;


    for (; groupIndex < unitCfgPtr->groupCountPerUnit; groupIndex++)
    {
        /* #10 get group configutation */
        groupCfgPtr = &adcConfigPtr->adcGroupCfgPtr[unitStartGroupId + groupIndex];

        /* #20 check whether group use dma to transfer */
        if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
        {
            /* #30 config dma params */
            /*PRQA S 2986  2*/
            dmaConfigRet = Dma_GetConfigParams(Adc_DmaUnitTable[unitCfgPtr->hwModulePhysicalId],
                    Adc_DmaSubIdTable[((uint8)DMA_ADC_FIFO0 + (uint8)groupCfgPtr->groupDmaChannelIndex)],
                    DMA_MODULE_ADC, &dmaAdcConfigData);

            AdcFaultInj_Adc_Ip_ConfigDmaGetParmFail();

            /* #40 check whether dma params config failed */
            if ((E_OK != dmaConfigRet ) || ((NULL_PTR == groupCfgPtr->notificationPtr)
                                            && (NULL_PTR == groupCfgPtr->groupDmaBufferPtr)))
            {
                /* dma params config failed */
                dmaCfgStatus = ADC_E_DMA_CFG_FAIL;
            }
            else
            {
                /* #50 request dma channel */
                chan = Dma_RequestChannelWithId(dmaAdcConfigData.controller, dmaAdcConfigData.channelId);

                AdcFaultInj_Adc_Ip_ConfigDmaReqChnlFail();

                /* #60 check whether request dma channel successfully */
                if (NULL_PTR == chan)
                {
                    /* #70 request dma channel failed */
                    dmaCfgStatus = ADC_E_DMA_CFG_FAIL;
                }
                else
                {
                    /* #80 detailed dma channel configuration */
                    /* adc1/3/5/7 -> dma1_mux  adc2/4/6 -> dma2_mux */
                    muxIdBase =
                        (((uint16)(unitCfgPtr->hwModulePhysicalId) % 2U) == 0U) ? ADC_ODD_DMA_START_MUX_ID : ADC_EVEN_DMA_START_MUX_ID;
                    adcDmaIdx = (uint16)(unitCfgPtr->hwModulePhysicalId) / 2U;
                    (void)Dma_InitConfigChannel(&dmaDetailCfg);
                    /*PRQA S 0314  1*/
                    groupCfgPtr->priv = (void *)chan;
                    /*PRQA S 0314  1*/
                    chan->context = (void *)groupCfgPtr;

                    if (groupCfgPtr->notificationPtr == NULL_PTR)
                    {
                        chan->irqCallback = NULL;
                        dmaDetailCfg.transferMode = DMA_TRANSFER_MODE_CONTINUOUS;
                        dmaDetailCfg.bufferMode = DMA_CIRCULAR_BUFFER;
                        dmaDetailCfg.loopMode = DMA_LOOP_MODE_1;
                        dmaDetailCfg.transaction = DMA_CYCLIC;
                        dmaDetailCfg.processMode = DMA_POLLING;
                        dmaDetailCfg.periodLength = (uint32)groupCfgPtr->channelCount * 4U;
                        /*PRQA S 0488  2*/
                        /*PRQA S 0306  2*/
                        dmaDetailCfg.dstAddress =
                                            Mcal_AddressConvert((uint32)groupCfgPtr->groupDmaBufferPtr);

                    }
                    else
                    {
                        chan->irqCallback = (Dma_IrqHandle)Adc_EndGroupConversionDma;
                        dmaDetailCfg.transferMode = DMA_TRANSFER_MODE_SINGLE;
                        dmaDetailCfg.bufferMode = DMA_SINGLE_BUFFER;
                        dmaDetailCfg.transaction = DMA_DEVICE;
                        dmaDetailCfg.processMode = DMA_INTERRUPT;
                        /*PRQA S 0488  4*/
                        /*PRQA S 0306  3*/
                        dmaDetailCfg.dstAddress =
                            Mcal_AddressConvert((uint32)(Adc_DmaBufAdcUnit +
                            ((uint8)groupCfgPtr->belongUnitPhysicalId * ADC_DMA_PER_UNIT_CHNL_CNT) +
                            (uint8)groupCfgPtr->groupDmaChannelIndex));
                    }

                    dmaDetailCfg.direction = DMA_DEVICE_TO_MEMORY;
                    dmaDetailCfg.srcAddress =
                                (uint32)Adc_BaseAddress[(uint8)unitCfgPtr->hwModulePhysicalId] +
                                            SADC_CONV_LOW_BASE((uint32)groupCfgPtr->groupRcRchtIndex);
                    dmaDetailCfg.srcBusWidth = DMA_BEAT_SIZE_4_BYTE;
                    dmaDetailCfg.dstBusWidth = DMA_BEAT_SIZE_4_BYTE;
                    dmaDetailCfg.srcMaxBurst = DMA_BURST_LENGTH_1;
                    dmaDetailCfg.dstMaxBurst = DMA_BURST_LENGTH_1;
                    dmaDetailCfg.srcPortSelect = DMA_PORT_AHB32;
                    dmaDetailCfg.dstPortSelect = DMA_PORT_AXI64;
                    dmaDetailCfg.srcIncDirection = DMA_BURST_FIXED;
                    dmaDetailCfg.dstIncDirection = DMA_BURST_INCREMENTAL;
                    dmaDetailCfg.flowControl = DMA_DIR_DEVICE_TO_MEMORY;
                    dmaDetailCfg.linkListTriggerMode = DMA_TRIGGER_BY_HARDWARE;
                    dmaDetailCfg.customMuxIdFlag = (boolean)TRUE;
                    dmaDetailCfg.customMuxId =
                                muxIdBase + (adcDmaIdx * 2U) + (uint16)groupCfgPtr->groupDmaChannelIndex;

                    AdcFaultInj_Adc_Ip_ConfigDmaCfgChnlFail();

                    /* #90 check whether dma channel config failed */
                    if (E_OK != Dma_ConfigChannel(chan, &dmaDetailCfg))
                    {
                        /* dma channel config failed */
                        dmaCfgStatus = ADC_E_DMA_CFG_FAIL;
                    }

                    /* #100 check whether dma prepare transmission failed */
                    else
                    {
                        if (groupCfgPtr->notificationPtr == NULL_PTR)
                        {
                            if (E_OK != Dma_PrepareTransmission(chan,
                                (((uint32)groupCfgPtr->channelCount * 4U) * groupCfgPtr->samplingTime)))
                            {
                                /* dma prepare transmission failed */
                                dmaCfgStatus = ADC_E_DMA_CFG_FAIL;
                            }
                        }
                        else
                        {
                            if (E_OK != Dma_PrepareTransmission(chan,
                                                        ((uint32)groupCfgPtr->channelCount + 1U) * 4U))
                            {
                                /* dma prepare transmission failed */
                                dmaCfgStatus = ADC_E_DMA_CFG_FAIL;
                            }
                        }
                    }
                }
            }
        }

        /* dma config failed */
        if (ADC_E_DMA_CFG_FAIL == dmaCfgStatus)
        {
            break;
        } /* else not needed */
    }

    return dmaCfgStatus;
}
#if (ADC_DEINIT_API == STD_ON) /* AdcDeInitApi enabled */
/********************************************************************************************************
 * \brief deinit dma.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_DeInitDma(const Adc_HwUnitType hwLogicalModuleId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : hwLogicalModuleId

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : deinit dma.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_DeInitDma(const Adc_HwUnitType hwLogicalModuleId)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const* coreHandlerPtr = Adc_Handler[coreId];
    /* hardware unit configuration */
    const Adc_HwUnitConfigType *unitCfgPtr =
                                    &(coreHandlerPtr->globalConfigPtr)->adcUnitCfgPtr[hwLogicalModuleId];
    /* group index */
    Adc_GroupType groupIndex = 0U;
    /* the first group id in current unit */
    Adc_GroupType unitStartGroupId = unitCfgPtr->startGroupIdInUnit;
    /* group configuration */
    const Adc_GroupConfigType *groupCfgPtr;
    /* dma deinit status */
    Adc_ErrorIdType dmaDeinitStatus = 0U;

    for (; groupIndex < unitCfgPtr->groupCountPerUnit; groupIndex++)
    {
        /* #10 get group configutation */
        groupCfgPtr = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[unitStartGroupId + groupIndex];

        /* #20 check whether group use dma to transfer */
        if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
        {
            AdcFaultInj_Adc_Ip_DmaReleaseFail();
            /* #30 release dma channel */
            /*PRQA S 0316  1*/
            if (E_OK != Dma_ReleaseChannel((Dma_ChannelConfigType *)groupCfgPtr->priv))
            {
                dmaDeinitStatus = ADC_E_DMA_RELEASE_FAIL;
                break;
            }
            else
            {
                dmaDeinitStatus = ADC_NO_ERROR;
            }
        }
        else
        {
            dmaDeinitStatus = ADC_NO_ERROR;
        }
    }

    return dmaDeinitStatus;
}
#endif /* #if (ADC_DEINIT_API == STD_ON) */
/********************************************************************************************************
 * \brief start dma Transmission.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_StartDmaTransmission(Adc_GroupType dmaGroup)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : dmaGroup

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : start dma Transmission.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_StartDmaTransmission(Adc_GroupType dmaGroup)
{
    Adc_ErrorIdType dmaCfgStatus = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const* coreHandlerPtr = Adc_Handler[coreId];
    const Adc_GroupConfigType *dmaGroupCfgPtr = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[dmaGroup];
    /* init buffer */
    Adc_Ip_InitBuffer(Adc_DmaBufAdcUnit[((uint8)dmaGroupCfgPtr->belongUnitPhysicalId *
                      ADC_DMA_PER_UNIT_CHNL_CNT) + (uint8)dmaGroupCfgPtr->groupDmaChannelIndex],
                      ((uint8)dmaGroupCfgPtr->channelCount + 2U) * 4U, 0x00UL);
#if (ADC_NO_CACHEABLE_NEEDED == STD_OFF)
    /*PRQA S 0306  1*/
    (void)Mcal_CleanCache((uint32) Adc_DmaBufAdcUnit[((uint8)dmaGroupCfgPtr->belongUnitPhysicalId *
                    ADC_DMA_PER_UNIT_CHNL_CNT) + (uint8)dmaGroupCfgPtr->groupDmaChannelIndex],
                    ((uint32)dmaGroupCfgPtr->channelCount + 1U) * 4U);
#endif /* #if (ADC_NO_CACHEABLE_NEEDED == STD_OFF) */
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_09();
    AdcFaultInj_Adc_Ip_StartDmaStatusFail();
    if (FALSE ==
        Adc_DmaTransStatus[dmaGroupCfgPtr->belongUnitPhysicalId][dmaGroupCfgPtr->groupDmaChannelIndex])
    {
        Adc_DmaTransStatus[dmaGroupCfgPtr->belongUnitPhysicalId][dmaGroupCfgPtr->groupDmaChannelIndex] =
            TRUE;
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_09();
        AdcFaultInj_Adc_Ip_DmaStartFail();
        /*PRQA S 0316  1*/
        if (E_OK != Dma_Start((Dma_ChannelConfigType *)dmaGroupCfgPtr->priv))
        {
            Adc_DmaTransStatus[dmaGroupCfgPtr->belongUnitPhysicalId][dmaGroupCfgPtr->groupDmaChannelIndex] =
                FALSE;
            dmaCfgStatus = ADC_E_DMA_START_FAIL;
        } /* else not needed */
    }
    else
    {
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_09();
    }

    return dmaCfgStatus;
}

/********************************************************************************************************
 * \brief stop dma Transmission.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_StopDmaTransmission(Adc_GroupType dmaGroup)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : dmaGroup

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : stop dma Transmission.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_StopDmaTransmission(Adc_GroupType dmaGroup)
{
    Adc_ErrorIdType dmaCfgStatus = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    const Adc_GroupConfigType *dmaGroupCfgPtr = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[dmaGroup];
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_09();

    if (TRUE ==
        Adc_DmaTransStatus[dmaGroupCfgPtr->belongUnitPhysicalId][dmaGroupCfgPtr->groupDmaChannelIndex])
    {
        Adc_DmaTransStatus[dmaGroupCfgPtr->belongUnitPhysicalId][dmaGroupCfgPtr->groupDmaChannelIndex] =
            FALSE;
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_09();
        AdcFaultInj_Adc_Ip_DmaStopFail();
        /*PRQA S 0316  1*/
        if (E_OK != Dma_Stop((Dma_ChannelConfigType *)dmaGroupCfgPtr->priv))
        {
            Adc_DmaTransStatus[dmaGroupCfgPtr->belongUnitPhysicalId][dmaGroupCfgPtr->groupDmaChannelIndex] =
                TRUE;
            dmaCfgStatus = ADC_E_DMA_STOP_FAIL;
        } /* else not needed */
    }
    else
    {
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_09();
    }

    return dmaCfgStatus;
}
#endif /* AdcEnableDmaTransferMode enabled */
#if (ADC_DEINIT_API == STD_ON) /* AdcDeInitApi enabled */
/********************************************************************************************************
 * \brief This function reset ADC controller.

 * \verbatim
 * Syntax             : static void Adc_Ip_DeInitUnit(
 *                          Adc_HwUnitType hwUnitIndex)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : hwUnitIndex - ADC controller logical ID

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function reset ADC controller.
 * \endverbatim
 * Traceability       : SWSR_ADC_191
 *******************************************************************************************************/
static void Adc_Ip_DeInitUnit(Adc_HwUnitType hwUnitIndex)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    /* adc unit base address */
    Adc_RegisterBaseType base =
        Adc_BaseAddress[coreHandlerPtr->globalConfigPtr->adcUnitCfgPtr[hwUnitIndex].hwModulePhysicalId];
    /* rc index */
    uint8 rcIndex = 0U;
    /* fifo count */
    uint8 fifoCount = 0U;
    /* rcht entry count */
    uint8 rchtEntryCount = 0U;
    /* rc entry count */
    uint8 rcEntryCount = 0U;
    /* unit analog register index */
    uint8 unitAnalogRegIndex = 0U;
    /* unit monitor register index */
    uint8 monitorIndex = 0U;
    /* times for read register */
    uint8 readTime = 0U;
    /* #30 reset the HTC ready_len */
    Adc_WriteRegister((base + SADC_HTC_BASE), SADC_HTC_READY_LEN_FIELD_OFFSET,
                      SADC_HTC_READY_LEN_FIELD_SIZE, ADC_HTC_READY_LEN_RESET_VALUE);
    /* #40 reset the HTC done_len */
    Adc_WriteRegister((base + SADC_HTC_BASE), SADC_HTC_DONE_LEN_FIELD_OFFSET,
                      SADC_HTC_DONE_LEN_FIELD_SIZE, ADC_HTC_DONE_LEN_RESET_VALUE);
    /* #50 reset scheduler master/slave mode bit */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_MST_MODE_FIELD_OFFSET,
                      SADC_SCH_CFG_MST_MODE_FIELD_SIZE, ADC_SCHEDULER_SLAVE_MASTER_MODE_RESET_VALUE);
    /* #60 reset scheduler async/sync mode */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_SYNC_MODE_FIELD_OFFSET,
                      SADC_SCH_CFG_SYNC_MODE_FIELD_OFFSET, ADC_SCHEDULER_ASYNC_SYNC_MODE_RESET_VALUE);
    /* #70 reset scheduler to disable the rotation */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_ROT_EN_FIELD_OFFSET,
                      SADC_SCH_CFG_ROT_EN_FIELD_SIZE, ADC_BIT_DISABLE);
    /* #80 reset timestamp */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_TS_RST_FIELD_OFFSET,
                      SADC_SCH_CFG_TS_RST_FIELD_SIZE, ADC_BIT_ENABLE);
    /* #90 release the reset of timestamp */
    Adc_WriteRegister((base + SADC_SCH_CFG_BASE), SADC_SCH_CFG_TS_RST_FIELD_OFFSET,
                      SADC_SCH_CFG_TS_RST_FIELD_SIZE, ADC_BIT_DISABLE);
    /* #110 reset dma */
    REG_WRITE32(ADC_DMA_CTRL_RESET_VALUE, base + SADC_DMA_BASE);

    /* #120 reset all RC timmers */
    for (; rcIndex < ADC_RC_TIMER_CNT; rcIndex++)
    {
        /* hold the reset */
        Adc_WriteRegister((base + SADC_SOFT_RST_BASE),
                            SADC_SOFT_RST_RC0_TMR_RST_FIELD_OFFSET + rcIndex,
                            SADC_SOFT_RST_EACH_RC_TMR_RST_FIELD_SIZE, ADC_BIT_ENABLE);
        /* release the reset */
        Adc_WriteRegister((base + SADC_SOFT_RST_BASE),
                            SADC_SOFT_RST_RC0_TMR_RST_FIELD_OFFSET + rcIndex,
                            SADC_SOFT_RST_EACH_RC_TMR_RST_FIELD_SIZE, ADC_BIT_DISABLE);
        /* reset rc timer compare/terminal value. */
        REG_WRITE32(0U, (base + SADC_RC_TIMER_BASE((uint32)rcIndex)));
        /* ready to clear cur_pointer. */
        Adc_WriteRegister((base + (SADC_RC_BASE((uint32)rcIndex))),
                            SADC_RC_SOFT_OVWR_POINT_EN_FIELD_OFFSET,
                            SADC_RC_SOFT_OVWR_POINT_EN_FIELD_SIZE, ADC_BIT_ENABLE);
        /* cur_pointer is set to 0. */
        Adc_WriteRegister((base + (SADC_RC_BASE((uint32)rcIndex))),
                            SADC_RC_CUR_POINT_FIELD_OFFSET,
                            SADC_RC_CUR_POINT_FIELD_SIZE, 0U);
        /* deinit rc */
        Adc_WriteRegister((base + SADC_RC_BASE((uint32)rcIndex)), SADC_RC_TRG_START_FIELD_OFFSET,
                          SADC_RC_TRG_START_FIELD_SIZE, ADC_BIT_DISABLE);
        Adc_WriteRegister((base + SADC_RC_BASE((uint32)rcIndex)), SADC_RC_TMR_MODE_FIELD_OFFSET,
                          SADC_RC_TMR_MODE_FIELD_SIZE, ADC_RC_TMR_MODE_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RC_BASE((uint32)rcIndex)), SADC_RC_TRG_MODE_FIELD_OFFSET,
                          SADC_RC_TRG_MODE_FIELD_SIZE, ADC_RC_TRG_MODE_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RC_BASE((uint32)rcIndex)), SADC_RC_TRG_EN_FIELD_OFFSET,
                          SADC_RC_TRG_EN_FIELD_SIZE, ADC_RC_TRG_EN_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RC_BASE((uint32)rcIndex)), SADC_RC_SOFT_TRG_TIMES_FIELD_OFFSET,
                          SADC_RC_SOFT_TRG_TIMES_FIELD_SIZE, ADC_RC_TRG_TIME_RESET_VALUE);
    }

    /* #130 reset fifo packmode */
    Adc_WriteRegister((base + SADC_FIFO_CFG_BASE),
                      SADC_FIFO_CFG_PACK_MODE_FIELD_OFFSET,
                      SADC_FIFO_CFG_PACK_MODE_FIELD_SIZE, ADC_FIFO_PACK_MODE_RESET_VALUE);

    /* #140 deinit all subfifo */
    for (; fifoCount < ADC_SUBFIFO_CNT; fifoCount++)
    {
        Adc_WriteRegister((base + SADC_SUB_FIFO_BASE((uint32)fifoCount)),
                          SADC_SUB_FIFO_SUB_START_FIELD_OFFSET,
                          SADC_SUB_FIFO_SUB_START_FIELD_SIZE, ADC_SUBFIFO_START_ADDR_RESET_VALUE);
        Adc_WriteRegister((base + SADC_SUB_FIFO_BASE((uint32)fifoCount)),
                          SADC_SUB_FIFO_SUB_THRD_FIELD_OFFSET,
                          SADC_SUB_FIFO_SUB_THRD_FIELD_SIZE, ADC_SUBFIFO_THRD_RESET_VALUE);
        Adc_WriteRegister((base + SADC_SUB_FIFO_BASE((uint32)fifoCount)),
                          SADC_SUB_FIFO_SUB_RC_EN_FIELD_OFFSET,
                          SADC_SUB_FIFO_SUB_RC_EN_FIELD_SIZE, ADC_SUBFIFO_EN_RCHT_RC_RESET_VALUE);
    }

    /* #150 deinit rcht entry */
    for (; rchtEntryCount < ADC_RCHT_ENTRY_CNT; rchtEntryCount++)
    {
        Adc_WriteRegister((base + SADC_RCHT_ENTRY_BASE((uint32)rchtEntryCount)),
                          SADC_RCHT_ENTRY_AMSEL_FIELD_OFFSET, SADC_RCHT_ENTRY_AMSEL_FIELD_SIZE,
                          ADC_RCHT_RC_ENTRY_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RCHT_ENTRY_BASE((uint32)rchtEntryCount)),
                            SADC_RCHT_ENTRY_CSEL_FIELD_OFFSET, SADC_RCHT_ENTRY_CSEL_FIELD_SIZE,
                            ADC_RCHT_RC_ENTRY_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RCHT_ENTRY_BASE((uint32)rchtEntryCount)),
                            SADC_RCHT_ENTRY_REPEAT_MODE_FIELD_OFFSET,
                            SADC_RCHT_ENTRY_REPEAT_MODE_FIELD_SIZE, ADC_RCHT_RC_ENTRY_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RCHT_ENTRY_BASE((uint32)rchtEntryCount)),
                            SADC_RCHT_ENTRY_REPEAT_TIMES_FIELD_OFFSET,
                            SADC_RCHT_ENTRY_REPEAT_TIMES_FIELD_SIZE, ADC_RCHT_RC_ENTRY_RESET_VALUE);
    }

    /* #160 deinit rc entry */
    for (; rcEntryCount < ADC_RC_ENTRY_TOTAL_CNT; rcEntryCount++)
    {
        Adc_WriteRegister((base + SADC_RC_ENTRY_BASE(((uint32)rcEntryCount / ADC_EACH_RC_ENTRY_CNT),
                           ((uint32)rcEntryCount % ADC_EACH_RC_ENTRY_CNT))),
                           SADC_RC_ENTRY_AMSEL_FIELD_OFFSET, SADC_RC_ENTRY_AMSEL_FIELD_SIZE,
                           ADC_RCHT_RC_ENTRY_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RC_ENTRY_BASE(((uint32)rcEntryCount / ADC_EACH_RC_ENTRY_CNT),
                           ((uint32)rcEntryCount % ADC_EACH_RC_ENTRY_CNT))),
                           SADC_RC_ENTRY_CSEL_FIELD_OFFSET, SADC_RC_ENTRY_CSEL_FIELD_SIZE,
                           ADC_RCHT_RC_ENTRY_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RC_ENTRY_BASE(((uint32)rcEntryCount / ADC_EACH_RC_ENTRY_CNT),
                           ((uint32)rcEntryCount % ADC_EACH_RC_ENTRY_CNT))),
                           SADC_RC_ENTRY_REPEAT_MODE_FIELD_OFFSET, SADC_RC_ENTRY_REPEAT_MODE_FIELD_SIZE,
                           ADC_RCHT_RC_ENTRY_RESET_VALUE);
        Adc_WriteRegister((base + SADC_RC_ENTRY_BASE(((uint32)rcEntryCount / ADC_EACH_RC_ENTRY_CNT),
                           ((uint32)rcEntryCount % ADC_EACH_RC_ENTRY_CNT))),
                           SADC_RC_ENTRY_REPEAT_TIMES_FIELD_OFFSET, SADC_RC_ENTRY_REPEAT_TIMES_FIELD_SIZE,
                           ADC_RCHT_RC_ENTRY_RESET_VALUE);
    }

    /* #170 reset analog register configuration */
    for (; unitAnalogRegIndex < ADC_CONFIG_ANA_REG_CNT; unitAnalogRegIndex++)
    {
        Adc_WriteRegister((base + SADC_ANA_PARA_BASE((uint32)unitAnalogRegIndex)),
                          SADC_ANA_PARA_REFSEL_FIELD_OFFSET,
                          SADC_ANA_PARA_REFSEL_FIELD_SIZE, ADC_VREREF_RESET_VALUE);
        Adc_WriteRegister((base + SADC_ANA_PARA_BASE((uint32)unitAnalogRegIndex)),
                          SADC_ANA_PARA_SAMCTRL_FIELD_OFFSET,
                          SADC_ANA_PARA_SAMCTRL_FIELD_SIZE, ADC_SAMPLE_CTRL_RESET_VALUE);
    }

    /* #180 reset monitor register configuration */
    for (; monitorIndex < ADC_MONITOR_CNT; monitorIndex++)
    {
        Adc_WriteRegister((base + SADC_MNT_THRD_SINGLE_BASE((uint32)monitorIndex)),
                          SADC_MNT_THRD_SINGLE_HTHRD_FIELD_OFFSET,
                          SADC_MNT_THRD_SINGLE_HTHRD_FIELD_SIZE, ADC_MONITOR_RESET_MASK_VALUE);
    }

    Adc_WriteRegister((base + SADC_MNT_THRD_CONT_BASE),
                      SADC_MNT_THRD_CONT_HTHRD_FIELD_OFFSET,
                      SADC_MNT_THRD_CONT_HTHRD_FIELD_SIZE, ADC_MONITOR_RESET_MASK_VALUE);
    /* disable all adc interrupts */
    /* #200 disable all adc int signals */
    REG_WRITE32(SADC_INT_SIG_EN_ALL, base + SADC_INT_SIG_EN_BASE);
    /* #210 disable all adc int status */
    REG_WRITE32(SADC_INT_STA_EN_ALL, base + SADC_INT_STA_EN_BASE);
    /* #220 clear all adc int status */
    REG_WRITE32(SADC_INT_STA_ALL, base + SADC_INT_STA_BASE);
    /* #230 reset adc initialzation value */
    Adc_WriteRegister((base + SADC_INIT_BASE), SADC_INIT_VALUE_FIELD_OFFSET,
                      SADC_INIT_VALUE_FIELD_SIZE, ADC_INIT_INITVALUE_RESET_AND_CONFIG_VALUE);
    /* #240 reset adc analog soft reset */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_ANA_RST_FIELD_OFFSET,
                      SADC_SOFT_RST_ANA_RST_FIELD_SIZE, ADC_BIT_DISABLE);
    /* #250 reset adc digital soft reset */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_DIG_RST_FIELD_OFFSET,
                      SADC_SOFT_RST_DIG_RST_FIELD_SIZE, ADC_BIT_ENABLE);
    /* #260 analog gate config */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_ANA_CLK_FORCE_CG_FIELD_OFFSET,
                      SADC_SOFT_RST_ANA_CLK_FORCE_CG_FIELD_SIZE, ADC_BIT_ENABLE);
    /* #270 release adc analog soft reset */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_ANA_RST_FIELD_OFFSET,
                      SADC_SOFT_RST_ANA_RST_FIELD_SIZE, ADC_BIT_ENABLE);

    for (; readTime < 10U; readTime ++)
    {
        REG_READ32(base + SADC_SOFT_RST_BASE);
    }

    /* #280 analog gate disable */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_ANA_CLK_FORCE_CG_FIELD_OFFSET,
                      SADC_SOFT_RST_ANA_CLK_FORCE_CG_FIELD_SIZE, ADC_BIT_DISABLE);
    /* #290 release adc digital soft reset */
    Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_DIG_RST_FIELD_OFFSET,
                      SADC_SOFT_RST_DIG_RST_FIELD_SIZE, ADC_BIT_DISABLE);
    return;
}
#endif /* AdcDeInitApi enabled */

/* normal code end */
#define ADC_STOP_SEC_CODE
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function clears adc fifo.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_ClearFifo(
 *                          Adc_RegisterBaseType unitBase,
 *                          Adc_TriggerSourceType trigSource,
 *                          boolean intFlag)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Reentrant

 * Parameters (in)    : unitBase - Adc Unit base address
 *                      trigSource - group trigger source
 *                      intFlag - flag indicates whether the function is called
 *                                in interrupt

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : clrFifoErrorStatus
 *                      0: No Error
 *                      ADC_E_FIFO_POLLING_TIMEOUT: bit set time out

 * Description        : This function clears adc fifo.
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
/* fast code function 14 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
static Adc_ErrorIdType Adc_Ip_ClearFifo(Adc_RegisterBaseType unitBase,
                                        uint8 subFifoIdx,
                                        boolean intFlag)
{
    /* #10 flush the fifo */
    Adc_WriteRegister((unitBase + SADC_SOFT_RST_BASE), SADC_FIFO_FLUSH(subFifoIdx),
                      SADC_FIFO_FLUSH_SIZE, ADC_BIT_ENABLE);
    Adc_WriteRegister((unitBase + SADC_SOFT_RST_BASE), SADC_FIFO_FLUSH(subFifoIdx),
                      SADC_FIFO_FLUSH_SIZE, ADC_BIT_DISABLE);
    /* prevent variable from no use */
    /* PRQA S 3119  2 */
    ADC_DUMMY_STATEMENT(intFlag);
    return ADC_NO_ERROR;
}
/* fast code function 14 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"


#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function update status for oneshot.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_UpdGrpStaForSingleOneShot(Adc_RegisterBaseType grpbelongUnitBase,
        Adc_GroupType singleOneGrpId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : grpbelongUnitBase
                        singleOneGrpId


 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function update status for oneshot.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_UpdGrpStaForSingleOneShot(Adc_RegisterBaseType grpbelongUnitBase,
        Adc_GroupType singleOneGrpId)
{
    /* dma start status */
    Adc_ErrorIdType dmaFailStatus = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
#if (ADC_HW_TRIGGER_API == STD_ON) /* AdcHwTriggerApi enabled */
    Adc_GroupConfigType singleOneGrpCfgPtr = coreHandlerPtr->globalConfigPtr->adcGroupCfgPtr[singleOneGrpId];
#endif /* AdcHwTriggerApi enabled */
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_08();
    coreHandlerPtr->allGrpInfo[singleOneGrpId].groupStatus = ADC_STREAM_COMPLETED;
    coreHandlerPtr->allGrpInfo[singleOneGrpId].groupConvFinishTime = 1U;
    coreHandlerPtr->allGrpInfo[singleOneGrpId].groupConvFinishIndex = 1U;
    coreHandlerPtr->allGrpInfo[singleOneGrpId].groupValueStatus = ADC_CONVERSION_UPDATE;
    /* exit critical zone */
    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_08();
#if (ADC_HW_TRIGGER_API == STD_ON) /* AdcHwTriggerApi enabled */

    if (ADC_TRIGG_SRC_HW == singleOneGrpCfgPtr.triggerSource)
    {
        /* enable next round conversion and record errorId */
        dmaFailStatus = Adc_Ip_TriggerEnable(grpbelongUnitBase, singleOneGrpId);
    } /* else not needed */

#endif /* AdcHwTriggerApi enabled */
    return dmaFailStatus;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"


#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function update status for single continue.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_UpdGrpStaForSingleConti(Adc_RegisterBaseType grpbelongUnitBase,
        Adc_GroupType singleContiGrpId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : grpbelongUnitBase
                        singleContiGrpId


 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function update status for single continue.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_UpdGrpStaForSingleConti(Adc_RegisterBaseType grpbelongUnitBase,
        Adc_GroupType singleContiGrpId)
{
    Adc_ErrorIdType dmaFailStatus;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_08();
    coreHandlerPtr->allGrpInfo[singleContiGrpId].groupStatus = ADC_STREAM_COMPLETED;
    coreHandlerPtr->allGrpInfo[singleContiGrpId].groupConvFinishTime = 1U;
    coreHandlerPtr->allGrpInfo[singleContiGrpId].groupConvFinishIndex = 1U;
    coreHandlerPtr->allGrpInfo[singleContiGrpId].groupValueStatus = ADC_CONVERSION_UPDATE;
    /* exit critical zone */
    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_08();
    /* enable next round conversion and record errorId */
    dmaFailStatus = Adc_Ip_TriggerEnable(grpbelongUnitBase, singleContiGrpId);
    return dmaFailStatus;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function update status for Linearbuffer.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_UpdGrpStaForLinear(
 *                                                              Adc_RegisterBaseType grpbelongUnitBase,
 *                                                              Adc_GroupType linearGrpId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : grpbelongUnitBase
                        linearGrpId


 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function update status for Linearbuffer.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_UpdGrpStaForLinear(Adc_RegisterBaseType grpbelongUnitBase,
        Adc_GroupType linearGrpId)
{
    Adc_ErrorIdType dmaFailStatus = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    Adc_GroupConfigType linearGrpCfgPtr = coreHandlerPtr->globalConfigPtr->adcGroupCfgPtr[linearGrpId];
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_08();
    coreHandlerPtr->allGrpInfo[linearGrpId].groupConvFinishTime += 1U;
    coreHandlerPtr->allGrpInfo[linearGrpId].groupConvFinishIndex += 1U;
    coreHandlerPtr->allGrpInfo[linearGrpId].groupValueStatus = ADC_CONVERSION_UPDATE;

    if (linearGrpCfgPtr.samplingTime > coreHandlerPtr->allGrpInfo[linearGrpId].groupConvFinishTime)
    {
        coreHandlerPtr->allGrpInfo[linearGrpId].groupStatus = ADC_COMPLETED;
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_08();
        /* enable next round conversion and record errorId */
        dmaFailStatus = Adc_Ip_TriggerEnable(grpbelongUnitBase, linearGrpId);
    }
    else
    {
        coreHandlerPtr->allGrpInfo[linearGrpId].groupStatus = ADC_STREAM_COMPLETED;
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_08();
    }

    return dmaFailStatus;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function update status for Circularbuffer.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_UpdGrpStaForCircular(
 *                                                              Adc_RegisterBaseType grpbelongUnitBase,
 *                                                              Adc_GroupType cricularGrpId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : grpbelongUnitBase
                        cricularGrpId


 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function update status for Circularbuffer.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_UpdGrpStaForCircular(Adc_RegisterBaseType grpbelongUnitBase,
        Adc_GroupType cricularGrpId)
{
    Adc_ErrorIdType dmaFailStatus;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    const Adc_GroupConfigType *circularGrpCfgPtr = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[cricularGrpId];
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_08();
    coreHandlerPtr->allGrpInfo[cricularGrpId].groupConvFinishTime += 1U;
    coreHandlerPtr->allGrpInfo[cricularGrpId].groupConvFinishIndex += 1U;
    coreHandlerPtr->allGrpInfo[cricularGrpId].groupValueStatus = ADC_CONVERSION_UPDATE;

    if (circularGrpCfgPtr->samplingTime > coreHandlerPtr->allGrpInfo[cricularGrpId].groupConvFinishTime)
    {
        coreHandlerPtr->allGrpInfo[cricularGrpId].groupStatus = ADC_COMPLETED;
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_08();
        /* enable next round conversion and record errorId */
        dmaFailStatus = Adc_Ip_TriggerEnable(grpbelongUnitBase, cricularGrpId);
    }
    else
    {
        coreHandlerPtr->allGrpInfo[cricularGrpId].groupStatus = ADC_STREAM_COMPLETED;
        coreHandlerPtr->allGrpInfo[cricularGrpId].groupConvFinishTime = circularGrpCfgPtr->samplingTime;
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_08();
        /* enable next round conversion and record errorId */
        dmaFailStatus = Adc_Ip_TriggerEnable(grpbelongUnitBase, cricularGrpId);
    }

    return dmaFailStatus;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"


#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function gets core id information.

 * \verbatim
 * Syntax             : Adc_CoreIdType Adc_Ip_GetCoreId(void)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : None

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       :core id information

 * Description        : This function gets core id information.
 * \endverbatim
 * Traceability       :
 *******************************************************************************************************/
Adc_CoreIdType Adc_Ip_GetCoreId(void)
{
    /* get core id */
    Adc_CoreIdType core = (Adc_CoreIdType)Mcal_GetCpuIndex();
    return core;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* normal code start */
#define ADC_START_SEC_CODE
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function init Adc driver in Ip level.

 * \verbatim
 * Syntax             : Adc_ErrorIdType Adc_Ip_Init(
 *                          const Adc_ConfigType* adcIpCfgPtr)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcIpCfgPtr - Pointer to configuration set

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ADC_NO_ERROR:   no error
 *                      Others:         config failed

 * Description        : This function init Adc driver in Ip level
 * \endverbatim
 * Traceability       : SWSR_ADC_053 SWSR_ADC_054 SWSR_ADC_055
 *******************************************************************************************************/
Adc_ErrorIdType Adc_Ip_Init(const Adc_ConfigType *adcIpCfgPtr)
{
    /* hardware Unit index */
    Adc_HwUnitType uintIndex = 0U;
    /* error code number */
    Adc_ErrorIdType errorStatus = 0U;
    /* core id num */
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
#if (ADC_DMA_SUPPORTED == STD_ON)
    /* group index */
    Adc_GroupType groupIndex = 0U;
#endif
    /* set apda mux relationship */
    Adc_Ip_ApdaCtrl();
    /* load trimed value */
    Adc_Ip_TrimValue();
    /* init adc clock config */
    Adc_Ip_ClkConfig(adcIpCfgPtr);
    /* init the adc unit */
    for (; uintIndex < adcIpCfgPtr->unitCount; uintIndex++)
    {
        /* init the adc hw uint by coreself */
        if (coreId == adcIpCfgPtr->adcUnitCfgPtr[uintIndex].coreAllocatedUint)
        {
            /* #20 config hw unit */
            Adc_Ip_ConfigUnit(adcIpCfgPtr, uintIndex);
            /* #30 config group,meanwhile,entry will be configured */
            Adc_Ip_ConfigGroup(adcIpCfgPtr, uintIndex);
            /* #30 config unit analog */
            Adc_Ip_ConfigAnalog(adcIpCfgPtr, uintIndex);
            
            /* #40 reset digital and analog */
            if (ADC_E_INIT_FAIL == Adc_Ip_ConfigReset(adcIpCfgPtr, uintIndex))
            {
                /* init time out */
                errorStatus = ADC_E_INIT_FAIL;
            }

#if (ADC_DMA_SUPPORTED == STD_ON)
            /* 50 check whether current unit needs dma */
            else if (ADC_UNIT_DMA_USED == adcIpCfgPtr->adcUnitCfgPtr[uintIndex].unitDmaUsed)
            {
                /* 60 check whether dma resourses are allocated successfully */
                if (ADC_E_DMA_CFG_FAIL == Adc_Ip_ConfigDma(adcIpCfgPtr,
                        adcIpCfgPtr->adcUnitCfgPtr[uintIndex].hwModuleIndex))
                {
                    errorStatus = ADC_E_DMA_CFG_FAIL;
                } /* else not needed */
            }
            else
            {
                /* do nothing */
            }

            /* check whether loop needed to be end */
            if (0U != errorStatus)
            {
                break;
            }

#endif /* #if (ADC_DMA_SUPPORTED == STD_ON) */
        }
    }

#if (ADC_DMA_SUPPORTED == STD_ON)

    /* Dma config fail happened */
    if (ADC_E_DMA_CFG_FAIL == errorStatus)
    {
        for (; groupIndex < adcIpCfgPtr->groupCountAllUnit; groupIndex++)
        {
            /* release the dma channel by coreself */
            if ((adcIpCfgPtr->adcGroupCfgPtr[groupIndex].coreAllocatedGrp == coreId) &&
                (adcIpCfgPtr->adcGroupCfgPtr[groupIndex].groupTransferType == ADC_DMA_MODE) &&
                (adcIpCfgPtr->adcGroupCfgPtr[groupIndex].priv != NULL_PTR))
            {
                /* release Dma channel */
                /*PRQA S 0316  3*/
                (void)Dma_ReleaseChannel(
                                (Dma_ChannelConfigType *)adcIpCfgPtr->adcGroupCfgPtr[groupIndex].priv);
            }
        }

        errorStatus = ADC_E_INIT_FAIL;
    }

#endif /* #if (ADC_DMA_SUPPORTED == STD_ON) */

    return errorStatus;
}
#if (ADC_DEINIT_API == STD_ON) /* AdcDeInitApi enabled */
/********************************************************************************************************
 * \brief This function returns Adc register to power set state.

 * \verbatim
 * Syntax             : Adc_ErrorIdType Adc_Ip_DeInit(
 *                          void)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : None

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ADC_E_FIFO_POLLING_TIMEOUT: Fifo clear time out
 *                      Other: No error

 * Description        : This function returns Adc register to power set state.
 * \endverbatim
 * Traceability       : SWSR_ADC_067
 *******************************************************************************************************/
Adc_ErrorIdType Adc_Ip_DeInit(void)
{
    Adc_ErrorIdType errorStatus = 0U;
    /* hardware Unit index */
    Adc_HwUnitType uintIndex = 0;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];

#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
    /* #10 reset adc analog part to full power state */
    Adc_Ip_SetPowerState(ADC_FULL_POWER);
#endif /* #if (ADC_POWER_STATE_SUPPORTED == STD_ON) */

    for (; uintIndex < coreHandlerPtr->globalConfigPtr->unitCount; uintIndex++)
    {
        if (coreId == coreHandlerPtr->globalConfigPtr->adcUnitCfgPtr[uintIndex].coreAllocatedUint)
        {
#if (ADC_DMA_SUPPORTED == STD_ON) /* AdcEnableDmaTransferMode enabled */
            /* #20 release all dma resources */
            if (ADC_NO_ERROR != Adc_Ip_DeInitDma(uintIndex))
            {
                errorStatus = ADC_E_DEINIT_FAIL;
            }
            else
#endif /* #if (ADC_DMA_SUPPORTED == STD_ON) */
            {
                /* #30 reset all adc register value */
                Adc_Ip_DeInitUnit(uintIndex);
            }
        }
    }

    return errorStatus;
}
#endif /* AdcDeInitApi enabled */
/* normal code end */
#define ADC_STOP_SEC_CODE
#include "Adc_MemMap.h"

#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) /* AdcEnableStartStopGroupApi enabled */
/* fast code function 17 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function starts all channels converison of the requested Adc group.

 * \verbatim
 * Syntax             : Adc_ErrorIdType Adc_Ip_StartGroupConversion(
 *                          Adc_GroupType ipGroupId)

 * Service ID[hex]    : None

 * Sync/Async         : Asynchronous

 * Reentrancy         : Reentrant

 * Parameters (in)    : ipGroupId - Numeric ID of requested ADC Channel group

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ADC_E_FIFO_POLLING_TIMEOUT: Fifo clear time out
 *                      Other: No error

 * Description        : This function starts all channels converison of the
 *                      requested Adc group.
 * \endverbatim
 * Traceability       : SWSR_ADC_074
 *******************************************************************************************************/
Adc_ErrorIdType Adc_Ip_StartGroupConversion(Adc_GroupType ipGroupId)
{
    /* error code number */
    Adc_ErrorIdType errorStatus = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    /* group configuration */
    const Adc_GroupConfigType *groupCfgPtr = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[ipGroupId];
    /* unit base address */
    Adc_RegisterBaseType base = Adc_BaseAddress[groupCfgPtr->belongUnitPhysicalId];
    /* rc/rcht select */
    uint8 rcRchtIdx = (uint8)groupCfgPtr->groupRcRchtIndex;
    /* rcht&rc0 share same subfifo, rc1/2/3 use independent sub_fifo1/2/3 */
    uint8 subFifoSel = (rcRchtIdx == 0u) ? rcRchtIdx : (rcRchtIdx - 1u);
    /* loop read time */
    uint8 readTime;
    /* interrupt sig en register val */
    uint32 sigEnVal;
    /* sw trigger status */
    uint32 swTrigSta;
    /* enable used ADC*/
    AdcFaultInj_Adc_Ip_SoftwareRst();
    if (0U != (REG_READ32(base + SADC_SOFT_RST_BASE) & (ADC_BIT_ENABLE <<
               SADC_SOFT_RST_FORCE_TURN_OFF_OFFSET)))
    {
        Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_FORCE_TURN_OFF_OFFSET,
                          SADC_SOFT_RST_FORCE_TURN_OFF_SIZE, ADC_BIT_DISABLE);

        /* wait 5 ctrl_clock */
        for (readTime = 0U; readTime < 10U; readTime ++)
        {
            REG_READ32(base + SADC_SOFT_RST_BASE);
        }
    }
#if (ADC_DMA_SUPPORTED == STD_ON)

    /* #10 check whether group is dma tranfer mode */
    if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
    {
        /* #20 start dma transmission */
        if (ADC_E_DMA_START_FAIL == Adc_Ip_StartDmaTransmission(ipGroupId))
        {
            /* start dma failed */
            errorStatus = ADC_E_START_FAIL;
        } /* else not needed */

        AdcFaultInj_Adc_Ip_TriggerEnableDmaStartFail();
    }
    else
#endif /* ADC_DMA_SUPPORTED == STD_ON */
    {
        /* interrupt transfer mode */
        (void)Adc_Ip_ClearFifo(base, subFifoSel, FALSE);
        /* get the sig_en value */
        sigEnVal = REG_READ32(base + SADC_INT_SIG_EN_BASE) & SADC_INT_SIG_EN_SUB_FIFO_ALL;
        /* #40 config adc subfifo0 connected to used RCx */
        Adc_WriteRegister(base + SADC_SUB_FIFO_BASE((uint32)ADC_SUBFIFO_ID(subFifoSel)),
                            SADC_SUB_FIFO_SUB_RC_EN_FIELD_OFFSET, SADC_SUB_FIFO_SUB_RC_EN_FIELD_SIZE,
                            0x1UL << (4U - rcRchtIdx));
        /* #50 config group fifo water mark number of channel in group */
        Adc_WriteRegister(base + SADC_SUB_FIFO_BASE((uint32)ADC_SUBFIFO_ID(subFifoSel)),
                            SADC_SUB_FIFO_SUB_THRD_FIELD_OFFSET,
                            SADC_SUB_FIFO_SUB_THRD_FIELD_SIZE, (uint32)groupCfgPtr->channelCount);
        /* #70 enable fifo watermark int status */
        Adc_WriteRegister(base + SADC_INT_STA_EN_BASE,
                            SADC_INT_STA_EN_SUB_FIFO_WML_OFFSET(subFifoSel),
                            SADC_INT_STA_EN_SUB_FIFO_SINGLE_FIELD_SIZE, ADC_BIT_ENABLE);
        if ((0x1UL << SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET(subFifoSel)) > sigEnVal)
        {
            /* Interrupts are guaranteed to be triggered by the lowest-priority rc/rcht */
            REG_WRITE32(0x1UL << SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET(subFifoSel), base + SADC_INT_SIG_EN_BASE);
        }
    }

    /* normal situation */
    /* PRQA S 2991,2995 2 */
    if (ADC_E_START_FAIL != errorStatus)
    {
        /* enter critical zone */
        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_00();
        if ((NULL_PTR == groupCfgPtr->notificationPtr) && (ADC_DMA_MODE == groupCfgPtr->groupTransferType))
        {

            /* set trg_start bit to enable rc timmer */
            Adc_WriteRegister(base + SADC_RC_BASE((uint32)groupCfgPtr->groupRcRchtIndex - 1U),
                              SADC_RC_TRG_START_FIELD_OFFSET,
                              SADC_RC_TRG_START_FIELD_SIZE, ADC_BIT_ENABLE);
            /* change group conversion status to not finished */
            coreHandlerPtr->allGrpInfo[ipGroupId].groupConvStatus = ADC_NOT_YET_FINISHED_CONVERTED;
        }
        /* normal mode */
        else
        {
            /* #80 check whether the software trigger is ready */
            swTrigSta = REG_READ32(base + SADC_RC_BASE((uint32)groupCfgPtr->groupRcRchtIndex - 1U));
            if ((swTrigSta >> SADC_RC_SOFT_TRG_DONE_STATUS_FIELD_OFFSET) == ADC_BIT_DISABLE)
            {
                errorStatus = ADC_E_START_FAIL;
            }
            else
            {
                AdcFaultInj_Adc_Ip_SoftwareTriggerStartFail();
                /* #90 set trg_start bit to enable rc timmer */
                Adc_WriteRegister(base + SADC_RC_BASE((uint32)groupCfgPtr->groupRcRchtIndex - 1U),
                                  SADC_RC_SOFT_TRG_FIELD_OFFSET,
                                  SADC_RC_SOFT_TRG_FIELD_SIZE, ADC_BIT_ENABLE);
                /* change group conversion status to not finished */
                coreHandlerPtr->allGrpInfo[ipGroupId].groupConvStatus = ADC_NOT_YET_FINISHED_CONVERTED;
            }
        }

        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_00();
        AdcFaultInj_Adc_Ip_StartInterruptPreemption();
    } /* else not needed */

    return errorStatus;
}
/* fast code function 17 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 18 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function stops all conversions of channels of the requested Adc Group.
 * \verbatim
 * Syntax             : Adc_ErrorIdType Adc_Ip_StopGroupConversion(
 *                          Adc_GroupType ipGroupId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Reentrant

 * Parameters (in)    : ipGroupId - Numeric ID of requested ADC Channel group

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ADC_E_FIFO_POLLING_TIMEOUT: Fifo clear time out
 *                      Others: No errors

 * Description        : This function stops all conversions of channels of the
 *                      requested Adc Group.
 * \endverbatim
 * Traceability       : SWSR_ADC_085 SWSR_ADC_087
 *******************************************************************************************************/
Adc_ErrorIdType Adc_Ip_StopGroupConversion(Adc_GroupType ipGroupId)
{
    /* error code number */
    Adc_ErrorIdType errorStatus = 0U;
    /* core id num */
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    /* group configuration */
    const Adc_GroupConfigType *groupCfgPtr = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[ipGroupId];
    /* unit base address */
    Adc_RegisterBaseType base = Adc_BaseAddress[groupCfgPtr->belongUnitPhysicalId];
    /* read reg time, 10 times cost about 1us */
    uint16 readRegTime = 0U;
    /* rc/rcht select */
    uint8 rcRchtIdx = (uint8)groupCfgPtr->groupRcRchtIndex;
    /* rcht&rc0 share same subfifo, rc1/2/3 use independent sub_fifo1/2/3 */
    uint8 subFifoSel = (rcRchtIdx == 0u) ? rcRchtIdx : (rcRchtIdx - 1u);
    /* sw trigger statue */
    uint32 swTrigSta;

    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01();

    /* #20 change group conversion status to finished */
    coreHandlerPtr->allGrpInfo[ipGroupId].groupConvStatus = ADC_ALREADY_FINISHED_CONVERTED;
    /* exit critical zone */
    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01();

    if ((NULL_PTR == groupCfgPtr->notificationPtr) && (ADC_DMA_MODE == groupCfgPtr->groupTransferType))
    {
        Adc_WriteRegister((base + SADC_RC_BASE(((uint32)rcRchtIdx - 1UL))),
                          SADC_RC_TRG_START_FIELD_OFFSET,
                          SADC_RC_TRG_START_FIELD_SIZE, 0U);
    }
    else
    {
        /* #30 wait for trigger times over */
        for (; readRegTime < (ADC_TRIGGER_LONGEST_TIME * groupCfgPtr->channelCount); readRegTime++)
        {
            /* #40 check whether the software trigger is ready */
            swTrigSta = REG_READ32(base + SADC_RC_BASE((uint32)rcRchtIdx - 1U));
            if ((swTrigSta >> SADC_RC_SOFT_TRG_DONE_STATUS_FIELD_OFFSET) == ADC_BIT_ENABLE)
            {
                /* wait trigger over successfully */
                errorStatus = 0U;
                break;
            }
            else
            {
                /* wait trigger over timeout */
                errorStatus = ADC_E_STOP_FAIL;
            }
        }
    }

    /* check if tigger disable failed already */
    if (errorStatus != ADC_E_STOP_FAIL)
    {
#if (ADC_DMA_SUPPORTED == STD_ON) /* AdcEnableDmaTransferMode enabled */

        /* #50 check whether group is dma tranfer mode */
        if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
        {
            /* #60 stop dma transmission */
            if (ADC_E_DMA_STOP_FAIL == Adc_Ip_StopDmaTransmission(ipGroupId))
            {
                /* stop dma transmission failed */
                errorStatus = ADC_E_STOP_FAIL;
            } /* else not needed */

            AdcFaultInj_Adc_Ip_TriggerDisableDmaStopFail();
        }
        else
#endif /* AdcEnableDmaTransferMode enabled */
        {
            /* interrupt tranfer mode */
            /* #70 config adc subfifo0 disconnected to used RCx */
            Adc_WriteRegister((base + SADC_SUB_FIFO_BASE((uint32)ADC_SUBFIFO_ID(subFifoSel))),
                              SADC_SUB_FIFO_SUB_RC_EN_FIELD_OFFSET,
                              SADC_SUB_FIFO_SUB_RC_EN_FIELD_SIZE,
                              0UL << (4U - rcRchtIdx));
            /* #80 clear int */
            Adc_ClearIntEnableAndStatus(base, ADC_BIT_ENABLE << SADC_INT_STA_SUB_FIFO_WML_OFFSET(subFifoSel));
            (void)Adc_Ip_ClearFifo(base, subFifoSel, FALSE);
        }

    }

    return errorStatus;
}
/* fast code function 18 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"
#endif /* AdcEnableStartStopGroupApi enabled */

#if (ADC_HW_TRIGGER_API == STD_ON) /* AdcHwTriggerApi enabled */
/* fast code function 19 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function enables the hardware trigger for the requested ADC Channel group
 *        in Ip level.

 * \verbatim
 * Syntax             : Adc_ErrorIdType Adc_Ip_EnableHardwareTrigger(
 *                          Adc_GroupType ipGroupId)

 * Service ID[hex]    : None

 * Sync/Async         : Asynchronous

 * Reentrancy         : Reentrant

 * Parameters (in)    : ipGroupId - Numeric ID of requested ADC Channel group

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ADC_E_FIFO_POLLING_TIMEOUT: Fifo clear time out
 *                      Others: No errors

 * Description        : This function enables the hardware trigger for the requested
 *                      ADC Channel group in Ip level.
 * \endverbatim
 * Traceability       : SWSR_ADC_167
 *******************************************************************************************************/
Adc_ErrorIdType Adc_Ip_EnableHardwareTrigger(Adc_GroupType ipGroupId)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    /* group configuration */
    const Adc_GroupConfigType *groupCfgPtr = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[ipGroupId];
    /* unit base address */
    Adc_RegisterBaseType base = Adc_BaseAddress[groupCfgPtr->belongUnitPhysicalId];
    /* error code number */
    Adc_ErrorIdType errorStatus = 0U;
    /* clk delay loop read time */
    uint8 readTime;
    /* interrupt sig en register val */
    uint32 sigEnVal;

    /* enable used ADC*/
    AdcFaultInj_Adc_Ip_SoftwareRst();
    if (0U != (REG_READ32(base + SADC_SOFT_RST_BASE) & (ADC_BIT_ENABLE <<
               SADC_SOFT_RST_FORCE_TURN_OFF_OFFSET)))
    {
        Adc_WriteRegister((base + SADC_SOFT_RST_BASE), SADC_SOFT_RST_FORCE_TURN_OFF_OFFSET,
                          SADC_SOFT_RST_FORCE_TURN_OFF_SIZE, ADC_BIT_DISABLE);

        /* wait 5 ctrl_clock */
        for (readTime = 0U; readTime < 10U; readTime ++)
        {
            REG_READ32(base + SADC_SOFT_RST_BASE);
        }
    }
#if (ADC_DMA_SUPPORTED == STD_ON) /* AdcEnableDmaTransferMode enabled */

    /* #10 check whether group is dma mode */
    if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
    {
        /* #20 start dma transmission */
        if (ADC_E_DMA_START_FAIL == Adc_Ip_StartDmaTransmission(ipGroupId))
        {
            /* start dma failed */
            errorStatus = ADC_E_START_FAIL;
        } /* else not needed */
    }
    else
#endif /* AdcEnableDmaTransferMode enabled */
    {
        /* interrupt tranfer mode */
        (void)Adc_Ip_ClearFifo(base, 0u, FALSE);
        /* get the sig_en value */
        sigEnVal = REG_READ32(base + SADC_INT_SIG_EN_BASE) & SADC_INT_SIG_EN_SUB_FIFO_ALL;
        /* #40 config adc subfifo0 connected to used rcht */
        Adc_WriteRegister(base + SADC_SUB_FIFO_BASE(ADC_SUBFIFO_ID(0u)),
                            SADC_SUB_FIFO_SUB_RC_EN_FIELD_OFFSET,
                            SADC_SUB_FIFO_SUB_RC_EN_FIELD_SIZE, (0x1UL << 0x4U));
        /* #50 config group fifo water mark number of channel in group */
        Adc_WriteRegister(base + SADC_SUB_FIFO_BASE(ADC_SUBFIFO_ID(0u)),
                            SADC_SUB_FIFO_SUB_THRD_FIELD_OFFSET,
                            SADC_SUB_FIFO_SUB_THRD_FIELD_SIZE, groupCfgPtr->channelCount);
        /* #70 enable fifo watermark int status */
        Adc_WriteRegister(base + SADC_INT_STA_EN_BASE, SADC_INT_STA_EN_SUB_FIFO_WML_OFFSET(0u),
                            SADC_INT_STA_EN_SUB_FIFO_SINGLE_FIELD_SIZE, ADC_BIT_ENABLE);
        if ((0x1UL << SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET(0u)) > sigEnVal)
        {
            /* Interrupts are guaranteed to be triggered by the lowest-priority rc/rcht */
            REG_WRITE32(0x1UL << SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET(0u), base + SADC_INT_SIG_EN_BASE);
        }
    }

    /* normal situation */
    /* PRQA S 2991,2995 2 */
    if (ADC_E_START_FAIL != errorStatus)
    {
        /* enter critical zone */
        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_02();
        /* #80 set sadc_htc ready 1 to ready for external trigger */
        /* when this bit is enable, hardware-triggered convertion will always be responsive */
        Adc_WriteRegister(base + SADC_HTC_BASE, SADC_HTC_READY_FIELD_OFFSET, SADC_HTC_READY_FIELD_SIZE, 1U);
        /* #90 change group conversion status to not finished */
        coreHandlerPtr->allGrpInfo[ipGroupId].groupConvStatus = ADC_NOT_YET_FINISHED_CONVERTED;
        /* exit critical zone */
        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_02();
        AdcFaultInj_Adc_Ip_StartInterruptPreemption();
    } /* else not needed */

    return errorStatus;
}
/* fast code function 19 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 20 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function disables the hardware trigger for the requested
 *        ADC Channel group.

 * \verbatim
 * Syntax             : Adc_ErrorIdType Adc_Ip_DisableHardwareTrigger(
 *                          Adc_GroupType ipGroupId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Reentrant

 * Parameters (in)    : ipGroupId - Numeric ID of requested ADC Channel group

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : ADC_E_FIFO_POLLING_TIMEOUT: Fifo clear time out
 *                      Others: No errors

 * Description        : This function disables the hardware trigger for the requested
 *                      ADC Channel group.
 * \endverbatim
 * Traceability       : SWSR_ADC_180
 *******************************************************************************************************/
Adc_ErrorIdType Adc_Ip_DisableHardwareTrigger(Adc_GroupType ipGroupId)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    /* group configuration */
    const Adc_GroupConfigType *groupCfgPtr = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[ipGroupId];
    /* unit base address */
    Adc_RegisterBaseType base = Adc_BaseAddress[groupCfgPtr->belongUnitPhysicalId];
    /* error code number */
    Adc_ErrorIdType errorStatus = 0U;
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_03();
    /* #20 change group conversion status to finished */
    coreHandlerPtr->allGrpInfo[ipGroupId].groupConvStatus = ADC_ALREADY_FINISHED_CONVERTED;
    /* exit critical zone */
    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_03();
#if (ADC_DMA_SUPPORTED == STD_ON) /* AdcEnableDmaTransferMode enabled */

    /* #30 check whether group is dma transfer mode */
    if (ADC_DMA_MODE == groupCfgPtr->groupTransferType)
    {
        /* #40 stop dma transmission */
        if (ADC_E_DMA_STOP_FAIL == Adc_Ip_StopDmaTransmission(ipGroupId))
        {
            /* stop dma transmission failed */
            errorStatus = ADC_E_STOP_FAIL;
        } /* else not needed */
    }
    else
#endif /* AdcEnableDmaTransferMode enabled */
    {
    /* interrupt transfer mode */
    /* #50 config adc subfifo0 disconnected to used rcht */
    Adc_WriteRegister(base + SADC_SUB_FIFO_BASE(ADC_SUBFIFO_ID(0u)),
                        SADC_SUB_FIFO_SUB_RC_EN_FIELD_OFFSET,
                        SADC_SUB_FIFO_SUB_RC_EN_FIELD_SIZE, (0UL << 4U));
    /* #60 clear int, rcht use sub_fifo default*/
    Adc_ClearIntEnableAndStatus(base, ADC_BIT_ENABLE << SADC_INT_STA_SUB_FIFO_WML_OFFSET(0u));
    (void)Adc_Ip_ClearFifo(base, 0u, FALSE);
    }
    return errorStatus;
}
/* fast code function 20 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"
#endif /* AdcHwTriggerApi enabled */

#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
static Adc_ErrorIdType Adc_CheckGroupStatusInInt(Adc_GroupType grpId)
{
    /* error code number */
    Adc_ErrorIdType errorStatus = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    /* #10 check whether group conversion status is already finished */
    if (ADC_ALREADY_FINISHED_CONVERTED == coreHandlerPtr->allGrpInfo[grpId].groupConvStatus)
    {
        /* the group should not trigger adc interrupt */
        errorStatus = ADC_E_INT_SOURCE;
    }
    /* #20 check whether group status is ADC_IDLE */
    else if (ADC_IDLE == coreHandlerPtr->allGrpInfo[grpId].groupStatus)
    {
        /* the group should not trigger adc interrupt */
        errorStatus = ADC_E_INT_SOURCE;
    }
    else
    {
        /* do nothing */
    }

    return errorStatus;
}
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* normal code start */
#define ADC_START_SEC_CODE
#include "Adc_MemMap.h"
#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON) /* AdcGrpNotifCapability enabled */
/********************************************************************************************************
 * \brief This function checks whether group notification is enabled or not.

 * \verbatim
 * Syntax             : static void Adc_CheckNotifInInterrupt(
 *                          Adc_GroupType grpNotifId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Reentrant

 * Parameters (in)    : grpNotifId - Numeric ID of requested ADC Channel group

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function checks whether group notification is enabled or not.
 * \endverbatim
 * Traceability       : SWSR_ADC_018 SWSR_ADC_157 SWSR_ADC_158 SWSR_ADC_159 SWSR_ADC_161
 *******************************************************************************************************/
static void Adc_CheckNotifInInterrupt(Adc_GroupType grpNotifId)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    /* #10 check whether group notification is enabled */
    if (ADC_NOTIFICATION_ENABLED == coreHandlerPtr->allGrpInfo[grpNotifId].groupNotifStatus)
    {
        /* #20 excute group notification if noitf is not NULL_PTR */
        if (NULL_PTR != coreHandlerPtr->globalConfigPtr->adcGroupCfgPtr[grpNotifId].notificationPtr)
        {
            coreHandlerPtr->globalConfigPtr->adcGroupCfgPtr[grpNotifId].notificationPtr();
        } /* else not needed */
    } /* else not needed */

    return;
}
#endif /* AdcGrpNotifCapability enabled */
/* normal code end */
#define ADC_STOP_SEC_CODE
#include "Adc_MemMap.h"

/* fast code function 13 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief Update status.

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_UpdateInInterrupt(
 *                                                              Adc_RegisterBaseType hardwareUnitbase,
 *                                                              Adc_GroupType grpStatusId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : hardwareUnitbase
                        grpStatusId

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : Update status.
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_UpdateInInterrupt(Adc_RegisterBaseType hardwareUnitbase,
        Adc_GroupType grpStatusId)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    /* group configuration */
    const Adc_GroupConfigType *grpCfg = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[grpStatusId];
    /* dma start status */
    Adc_ErrorIdType dmaError;

    /* #10 single access mode */
    if (ADC_ACCESS_MODE_SINGLE == grpCfg->groupAccessMode)
    {
        /* #20 one-shot mode */
        if (ADC_CONV_MODE_ONESHOT == grpCfg->groupConvMode)
        {
            /* update group status and record probable errorId */
            dmaError = Adc_UpdGrpStaForSingleOneShot(hardwareUnitbase, grpStatusId);
        }
        /* #30 continuous mode */
        else
        {
            /* update group status and record probable errorId */
            dmaError = Adc_UpdGrpStaForSingleConti(hardwareUnitbase, grpStatusId);
        }
    }
    /* #40 streaming access mode */
    else
    {
        /* #50 linear buffer mode */
        if (ADC_STREAM_BUFFER_LINEAR == grpCfg->strBufferMode)
        {
            /* update group status and record probable errorId */
            dmaError = Adc_UpdGrpStaForLinear(hardwareUnitbase, grpStatusId);
        }
        /* #60 circular buffer mode */
        else
        {
            /* update group status and record probable errorId */
            dmaError = Adc_UpdGrpStaForCircular(hardwareUnitbase, grpStatusId);
        }
    }

    return dmaError;
}
/* fast code function 13 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 11 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief normal conversion values process

 * \verbatim
 * Syntax             : static Adc_ErrorIdType Adc_Ip_NormalValueHandle(Adc_RegisterBaseType hwBase,
        Adc_GroupType ipGroupId,
        const Adc_ValueGroupType *valuePtr)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : hwBase
                        ipGroupId
                        valuePtr

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : errId

 * Description        : normal conversion values process
 * \endverbatim
 *******************************************************************************************************/
static Adc_ErrorIdType Adc_Ip_NormalValueHandle(Adc_RegisterBaseType hwBase,
        Adc_GroupType ipGroupId,
        const Adc_ValueGroupType *valuePtr)
{
    /* channel index */
    Adc_ChannelType chnlIndex = 0U;
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType *coreHandlerPtr = Adc_Handler[coreId];
    /* group configuration */
    const Adc_GroupConfigType *grpCfg = &(coreHandlerPtr->globalConfigPtr)->adcGroupCfgPtr[ipGroupId];
    /* dma start status */
    Adc_ErrorIdType dmaStartStatus;

    const Adc_ValueGroupType *tempValuePtr = valuePtr;
    /* enter critical zone */
    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_07();

    /* #10 check whether current finish index reaches target sample time */
    if (grpCfg->samplingTime == coreHandlerPtr->allGrpInfo[ipGroupId].groupConvFinishIndex)
    {
        /* #20 reset finish index */
        coreHandlerPtr->allGrpInfo[ipGroupId].groupConvFinishIndex = 0U;
    } /* else not needed */

    for (; chnlIndex < grpCfg->channelCount; chnlIndex++)
    {
        {
            /* #50 return normal conversion value to result buffer */
            grpCfg->bufferBasePtr[(chnlIndex * grpCfg->samplingTime) +
                                    coreHandlerPtr->allGrpInfo[ipGroupId].groupConvFinishIndex] = *tempValuePtr;
        }

        /* process next conversion value */
        tempValuePtr++;
    }

    /* #60 update group status and record probable errorId */
    dmaStartStatus = Adc_Ip_UpdateInInterrupt(hwBase, ipGroupId);
    /* exit critical zone */
    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_07();

    /* #70 check whether group notification is enabled */
    /* if enabled,excute group notification */
#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON) /* AdcGrpNotifCapability enabled */
    Adc_CheckNotifInInterrupt(ipGroupId);
#endif /* AdcGrpNotifCapability enabled */

    return dmaStartStatus;
}
/* fast code function 11 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* fast code function 10 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
static Adc_ErrorIdType Adc_Ip_ChnlValueHandle(Adc_RegisterBaseType unitBase, Adc_GroupType grpId,
        const Adc_ValueGroupType *checkValue)
{
    /* dma start status */
    Adc_ErrorIdType dmaStartStatus;

    {
        /* #50 normal conversion values process */
        dmaStartStatus = Adc_Ip_NormalValueHandle(unitBase, grpId, checkValue);
    }

    return dmaStartStatus;
}
/* fast code function 10 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* normal code start */
#define ADC_START_SEC_CODE
#include "Adc_MemMap.h"
static void Adc_ClearIntEnableAndStatus(Adc_RegisterBaseType hwUnitbase, Adc_RegisterValue regVal)
{
    /* interrupt sig en register val */
    uint32 staEnVal;
    /* interrupt sig en register val */
    uint32 staEnReg;
    /* sig_en register set loop */
    uint8 sigEnLoop = 0;
    /* clear the channel's interrupt */
    uint32 staClrVal = regVal;
    uint32 sigEnCtrlVal = (~regVal) & (REG_READ32(hwUnitbase + SADC_INT_SIG_EN_BASE));
    uint32 staEnCtrlVal = (~regVal) & (REG_READ32(hwUnitbase + SADC_INT_STA_EN_BASE));
    /* disable adc int signals */
    REG_WRITE32(sigEnCtrlVal, hwUnitbase + SADC_INT_SIG_EN_BASE);
    /* disable adc int status */
    REG_WRITE32(staEnCtrlVal, hwUnitbase + SADC_INT_STA_EN_BASE);
    /* clear adc int status */
    REG_WRITE32(staClrVal, hwUnitbase + SADC_INT_STA_BASE);
    staEnReg = (REG_READ32(hwUnitbase + SADC_INT_STA_EN_BASE) & SADC_INT_STA_EN_SUB_FIFO_ALL);
    staEnVal = staEnReg >> SADC_INT_STA_EN_SUB_FIFO_WML_OFFSET(0u);
    for(; sigEnLoop < ADC_SUBFIFO_CNT; sigEnLoop++)
    {
        /* 0x8: check if the highest bit in sub fifo is 1 */
        if (((staEnVal << sigEnLoop) & 0x8UL) != 0UL)
        {
            /* Interrupts are guaranteed to be triggered by the lowest-priority rc/rcht */
            REG_WRITE32(0x1UL << SADC_INT_SIG_EN_SUB_FIFO_WML_OFFSET(3U - sigEnLoop),
                                                        hwUnitbase + SADC_INT_SIG_EN_BASE);
            break;
        }
    }


}
/* normal code end */
#define ADC_STOP_SEC_CODE
#include "Adc_MemMap.h"

/* fast code function 16 start */
#define ADC_START_SEC_CODE_FAST
#include "Adc_MemMap.h"
/********************************************************************************************************
 * \brief This function is ISR for Adc Driver.

 * \verbatim
 * Syntax             : void Adc_EndGroupConversion(
 *                          Adc_HwUnitType hardwarePhysicalId)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Reentrant

 * Parameters (in)    : hardwarePhysicalId - Physical Id for Adc Unit

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function is ISR for Adc Driver.
 * \endverbatim
 * Traceability       : SWSR_ADC_155 SWSR_ADC_190
 *******************************************************************************************************/
void Adc_EndGroupConversion(Adc_HwUnitType hardwarePhysicalId)
{
    Adc_CoreIdType coreId = Adc_Ip_GetCoreId();
    Adc_CoreHandlerType const *coreHandlerPtr = Adc_Handler[coreId];
    /* error status in interrupt */
    Adc_ErrorIdType intErrorStatus = 0U;
    /* hardware Unit index */
    Adc_HwUnitType uintIndex;
    /* adc uinit base */
    Adc_RegisterBaseType base;
    /* adc group id which trigger interrupt */
    Adc_GroupType grpIdInInterrupt;
    /* internal buffer to save conversion values momentarily */
    Adc_ValueGroupType internalBuffer[ADC_USED_MAX_GROUP_CHNL_COUNT];
    /* converted flag buffer */
    Adc_ValueGroupType convFlag[ADC_USED_MAX_GROUP_CHNL_COUNT];
    /* check which group generate the interrupt */
    Adc_GroupType rcRchtIndex;
    /* group rcht/rc index */
    Adc_RegisterValue rcRchtIrqSta;
    /* sub_fifo0 status */
    Adc_RegisterValue subFifo0;
    /* sub fifo index */
    uint8 subFifoIdx;
    /* sub_fifo0 status */
    Adc_RegisterValue irqClrVal = SADC_INT_STA_ALL;
    /* get unit configuration */
    const Adc_HwUnitConfigType *hwCfgInInterrupt;
    /* init internal buffer with 0 */
    Adc_Ip_InitBuffer(internalBuffer, ADC_USED_MAX_GROUP_CHNL_COUNT, 0x00UL);
    AdcFaultInj_Adc_Ip_ErrorCore();
    for (uintIndex = 0; uintIndex < coreHandlerPtr->globalConfigPtr->unitCount; uintIndex++)
    {
        /* Check that the core that generated the interrupt is consistent with the configuration */
        if (((Adc_HwUnitType)coreHandlerPtr->globalConfigPtr->adcUnitCfgPtr[uintIndex].hwModulePhysicalId == hardwarePhysicalId) &&
            (coreHandlerPtr->globalConfigPtr->adcUnitCfgPtr[uintIndex].coreAllocatedUint != coreId))
        {
            intErrorStatus = ADC_E_PARAM_CORE;
            Adc_ClearIntEnableAndStatus(Adc_BaseAddress[hardwarePhysicalId], irqClrVal);
            break;
        }
    }
    if (intErrorStatus == 0U)
    {
        base = Adc_BaseAddress[hardwarePhysicalId];
        /* #10 check whether adc module is initialized */
        if (ADC_E_UNINIT == Adc_CheckInitNotYet())
        {
            intErrorStatus = ADC_E_UNINIT;
            /* clear all interrupt */
            Adc_ClearIntEnableAndStatus(base, irqClrVal);
        }
        else
        {
            hwCfgInInterrupt = Adc_GetHwCfgThroughPhysicalId(hardwarePhysicalId);

            /* #20 check the unit triggers interrupt whether is configured */
            if (NULL_PTR == hwCfgInInterrupt)
            {
                intErrorStatus = ADC_E_TRIG_INT_ID;
                /* clear all interrupt */
                Adc_ClearIntEnableAndStatus(base, irqClrVal);
            }
            else
            {
                /* #30 check whether adc interrupt signal register is enabled */
                if (ADC_E_INT_NOT_ENABLE == Adc_InterruptEnableCheck(base))
                {
                    intErrorStatus = ADC_E_INT_NOT_ENABLE;
                    /* clear all interrupt */
                    Adc_ClearIntEnableAndStatus(base, irqClrVal);
                }
                else
                {
                    /* #40 get rcht/rc index through fifo configuration */
                    rcRchtIrqSta = Adc_Ip_GetInterruptBit(base);
                    for(subFifoIdx = 0u; subFifoIdx < ADC_SUBFIFO_CNT; subFifoIdx++)
                    {
                        if (((rcRchtIrqSta >> subFifoIdx) & ADC_BIT_ENABLE) == ADC_BIT_ENABLE)
                        {
                            /* init converted flag buffer with 0 */
                            Adc_Ip_InitBuffer(convFlag, ADC_USED_MAX_GROUP_CHNL_COUNT, 0x00UL);
                            /* Clean up the interrupt corresponding to the sub_fifo */
                            irqClrVal = ADC_BIT_ENABLE << SADC_INT_STA_SUB_FIFO_WML_OFFSET(subFifoIdx);
                            /* rcht&rc0 share same subfifo, rc1/2/3 use independent sub_fifo1/2/3 */
                            rcRchtIndex = ((uint16)subFifoIdx + 1u);
                            if (subFifoIdx == 0u)
                            {
                                /* identify rc0 or rcht */
                                subFifo0 = REG_READ32(base + SADC_SUB_FIFO_BASE(ADC_SUBFIFO_ID(0u)));
                                rcRchtIndex =
                                 (((subFifo0 >> SADC_SUB_FIFO_SUB_RC_EN_RCHT_FIELD_OFFSET) & ADC_BIT_ENABLE) == ADC_BIT_ENABLE) ? subFifoIdx : rcRchtIndex;
                            } /* else not needed */
                            /* #50 get group id through rcht/rc index */
                            /* PRQA S 4342 3 */
                            grpIdInInterrupt = Adc_GetGrpIdThroughRcRchtIndex(hwCfgInInterrupt->startGroupIdInUnit,
                                            (Adc_RcRchtIndexType)rcRchtIndex);

                            /* #60 check whether group is in valid status */
                            if (ADC_E_INT_SOURCE == Adc_CheckGroupStatusInInt(grpIdInInterrupt))
                            {
                                /* group should not trigger interrupt */
                                intErrorStatus = ADC_E_INT_SOURCE;
                                Adc_ClearIntEnableAndStatus(base, irqClrVal);
                            }
                            /* group is in valid status */
                            else
                            {
                                /* #70 disable trigger and disconnect fifo */
                                (void)Adc_Ip_TriggerDisable(base, grpIdInInterrupt);

                                /* #80 check whether conversion values can match with group channels configuration */
                                if (ADC_E_VALUE_MATCH == Adc_Ip_ReadFifo(base, grpIdInInterrupt, internalBuffer, convFlag))
                                {
                                    /* not match */
                                    intErrorStatus = ADC_E_VALUE_MATCH;
                                    Adc_ClearIntEnableAndStatus(base, irqClrVal);
                                }
                                /* conversion values match */
                                else
                                {
                                    (void)Adc_Ip_ClearFifo(base, subFifoIdx, TRUE);

                                    /* 100 channel conversion values process */
                                    if (ADC_E_SW_TRIG_NOT_READY == Adc_Ip_ChnlValueHandle(base, grpIdInInterrupt,
                                            (const Adc_ValueGroupType *) internalBuffer))
                                    {
                                        /* software trigger bit is not ready */
                                        intErrorStatus = ADC_E_SW_TRIG_NOT_READY;
                                        Adc_ClearIntEnableAndStatus(base, irqClrVal);
                                    }
                                    else

                                    {

                                        /* normal situation */
                                        /* #110 clear int status */
                                        REG_WRITE32(irqClrVal, base + SADC_INT_STA_BASE);
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
    }
    AdcFaultInj_AdcFaultIntErrorStatus();
    /* PRQA S 3119  1 */
    ADC_DUMMY_STATEMENT(intErrorStatus);
    return;
}
/* fast code function 16 stop */
#define ADC_STOP_SEC_CODE_FAST
#include "Adc_MemMap.h"

/* normal code start */
#define ADC_START_SEC_CODE
#include "Adc_MemMap.h"
#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
/********************************************************************************************************
 * \brief This function change power state in ip level.

 * \verbatim
 * Syntax             : void Adc_Ip_SetPowerState(
 *                          Adc_PowerStateType targetPowerState)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : targetPowerState - power state ready to be set

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function change power state in ip level.
 * \endverbatim
 * Traceability       : SWSR_ADC_134 SWSR_ADC_191
 *******************************************************************************************************/
void Adc_Ip_SetPowerState(Adc_PowerStateType targetPowerState)
{
    /* time of reading register */
    uint32 rdRegTime;
    /* register offset */
    volatile uint32 regOffBase;
    /* adc hardware module index */
    uint8 adcHwModule;

    /* set all adc unit analog. */
    /* #10 target power is full power */
    if (ADC_FULL_POWER == targetPowerState)
    {
        /*PRQA S 2462  1*/
        for (adcHwModule = 0U; adcHwModule < ADC_MODULE_NUMBER; adcHwModule++)
        {
            /* get analog register offset */
            regOffBase = Adc_BaseAddress[adcHwModule] + SADC_ANA_REF_PART1_BASE;
            /* enable analog part */
            Adc_WriteRegister(regOffBase, SADC_ANA_REF_PART1_PD_OFFSET, SADC_ANA_REF_PART1_PD_SIZE, 0U);
            Adc_WriteRegister(regOffBase, SADC_ANA_REF_PART1_PDBIAS_OFFSET,
                                        SADC_ANA_REF_PART1_PDBIAS_SIZE, 0U);
            if (adcHwModule == (uint8)ADC_INDEX_ADC7)
            {
                /* ADC7: restore the clock configuration to 166M */
                Adc_WriteRegister(Adc_BaseAddress[adcHwModule] + SADC_CLK_CTRL_BASE,
                                  SADC_CLK_CTRL_DIV_BYPASS_FIELD_OFFSET,
                                  SADC_CLK_CTRL_DIV_BYPASS_FIELD_SIZE, 0U);
            }
            /* #20 ensure analog part has at least 100us to be ready */
            /* read register one time may cost at least 100ns */
            /* read 20000 times to ensure 100us has past */
            for (rdRegTime = 0U; rdRegTime < ADC_POLLING_TIMEOUT_VALUE; rdRegTime++)
            {
                (void)REG_READ32(Adc_BaseAddress[adcHwModule] + SADC_ANA_REF_PART1_BASE);
            }
        }
    }
    /* #30 target power is low power */
    else
    {
        /*PRQA S 2462,2982  1*/
        for (adcHwModule = 0U; adcHwModule < ADC_MODULE_NUMBER; adcHwModule++)
        {
            if (adcHwModule == (uint8)ADC_INDEX_ADC7)
            {
                /* ADC7: bypass the clock configuration to 24M */
                Adc_WriteRegister(Adc_BaseAddress[adcHwModule] + SADC_CLK_CTRL_BASE,
                                  SADC_CLK_CTRL_DIV_BYPASS_FIELD_OFFSET,
                                  SADC_CLK_CTRL_DIV_BYPASS_FIELD_SIZE, 1U);
            }
            else
            {
                /* ADC0 - ADC6: disable analog part, ADC7 needs maintain the power up state */
                Adc_WriteRegister(Adc_BaseAddress[adcHwModule] + SADC_ANA_REF_PART1_BASE,
                                SADC_ANA_REF_PART1_PD_OFFSET, SADC_ANA_REF_PART1_PD_SIZE, 1U);
                Adc_WriteRegister(Adc_BaseAddress[adcHwModule] + SADC_ANA_REF_PART1_BASE,
                                SADC_ANA_REF_PART1_PDBIAS_OFFSET, SADC_ANA_REF_PART1_PDBIAS_SIZE, 1U);
            }

        }
    }
}
#endif /* #if (ADC_POWER_STATE_SUPPORTED == STD_ON) */

/********************************************************************************************************
 * \brief This function enable CCT for reduce leakage.

 * \verbatim
 * Syntax             : void Adc_Ip_EnableCCT(Adc_HwModuleIndexType adcId, uint8 sampleTime, uint16 valueCCT)

 * Service ID[hex]    : None

 * Sync/Async         : Synchronous

 * Reentrancy         : Non reentrant

 * Parameters (in)    : adcId - 0:ADC1,1:ADC2,2:ADC3
                        sampleTime - ADC channel sampleTime control 0~7(meanning ref to SAMCTRL on TRM)
                        valueCCT - n means n+1 ana_clk

 * Parameters (inout) : None

 * Parameters (out)   : None

 * Return value       : None

 * Description        : This function enable CCT for reduce leakage.
                        When an adc samples multiple channels, some sampling high voltage and some
                        sampling low voltage, it is necessary to enable the CCT discharging after
                        Adc_Init, and valueCCT needs to be set to meet the conditions:
                        1) 1.5us <= valueCCT*ana_clk < samctrl*ana_clk
                        2) valueCCT as small as possible
 * \endverbatim
 *******************************************************************************************************/
void Adc_Ip_EnableCCT(Adc_HwModuleIndexType adcId, uint8 sampleTime, uint16 valueCCT)
{
    Adc_WriteRegister((Adc_BaseAddress[adcId] + SADC_ANA_PARA_BASE((uint32)sampleTime)),
                      SADC_ANA_PARA_CCP_FIELD_OFFSET, SADC_ANA_PARA_CCP_FIELD_SIZE, 3U);
    Adc_WriteRegister((Adc_BaseAddress[adcId] + SADC_ANA_PARA_BASE((uint32)sampleTime)),
                      SADC_ANA_PARA_CCN_FIELD_OFFSET, SADC_ANA_PARA_CCN_FIELD_SIZE, 3U);
    Adc_WriteRegister((Adc_BaseAddress[adcId] + SADC_ANA_PARA_BASE((uint32)sampleTime)),
                      SADC_ANA_PARA_CCT_FIELD_OFFSET, SADC_ANA_PARA_CCT_FIELD_SIZE, valueCCT);
}
#define ADC_STOP_SEC_CODE
#include "Adc_MemMap.h"

#ifdef __cplusplus
}
#endif
